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456f7ff8b2
change the ddr saved info to the last 16KB of the OCRAM. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
27 lines
637 B
Text
27 lines
637 B
Text
menu "i.MX9 DDR controllers"
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depends on ARCH_IMX9
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config IMX9_DRAM
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bool "imx9 dram"
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select IMX_SNPS_DDR_PHY
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config IMX9_LPDDR4X
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bool "imx9 lpddr4 and lpddr4x"
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select IMX9_DRAM
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help
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Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
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config IMX9_DRAM_PM_COUNTER
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bool "imx9 DDRC performance monitor counter"
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default y
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help
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Enable DDR controller performance monitor counter for reference events.
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config SAVED_DRAM_TIMING_BASE
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hex "Define the base address for saved dram timing"
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help
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after DRAM is trained, need to save the dram related timming
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info into memory for low power use.
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default 0x2051C000
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endmenu
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