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During NAND_SPL boot, base address and different register are programmed default by corresponding NAND controllers(eLBC/IFC). These settings are sufficient enough for NAND SPL. Avoid updating these register.They will be programmed during NAND RAMBOOT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
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arm | ||
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blackfin | ||
m68k | ||
microblaze | ||
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nds32 | ||
nios2 | ||
openrisc | ||
powerpc | ||
sandbox | ||
sh | ||
sparc | ||
x86 | ||
.gitignore |