mirror of
https://github.com/AsahiLinux/u-boot
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32cb2c70c4
Patch by JinHua Luo, 01 Sep 2005
219 lines
4.6 KiB
C
219 lines
4.6 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
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#include <arm920t.h>
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#if defined(CONFIG_S3C2400)
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#include <s3c2400.h>
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#elif defined(CONFIG_S3C2410)
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#include <s3c2410.h>
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#endif
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int timer_load_val = 0;
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/* macro to read the 16 bit timer */
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static inline ulong READ_TIMER(void)
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{
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S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
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return (timers->TCNTO4 & 0xffff);
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}
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static ulong timestamp;
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static ulong lastdec;
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int interrupt_init (void)
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{
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S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
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/* use PWM Timer 4 because it has no output */
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/* prescaler for Timer 4 is 16 */
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timers->TCFG0 = 0x0f00;
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if (timer_load_val == 0)
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{
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/*
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* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
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* (default) and prescaler = 16. Should be 10390
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* @33.25MHz and 15625 @ 50 MHz
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*/
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timer_load_val = get_PCLK()/(2 * 16 * 100);
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}
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/* load value for 10 ms timeout */
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lastdec = timers->TCNTB4 = timer_load_val;
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/* auto load, manual update of Timer 4 */
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timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
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/* auto load, start Timer 4 */
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timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
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timestamp = 0;
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return (0);
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}
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/*
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* timer without interrupts
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*/
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void reset_timer (void)
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{
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reset_timer_masked ();
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}
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ulong get_timer (ulong base)
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{
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return get_timer_masked () - base;
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}
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void set_timer (ulong t)
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{
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timestamp = t;
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}
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void udelay (unsigned long usec)
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{
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ulong tmo;
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ulong start = get_timer(0);
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tmo = usec / 1000;
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tmo *= (timer_load_val * 100);
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tmo /= 1000;
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while ((ulong)(get_timer_masked () - start) < tmo)
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/*NOP*/;
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}
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void reset_timer_masked (void)
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{
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/* reset time */
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lastdec = READ_TIMER();
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timestamp = 0;
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}
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ulong get_timer_masked (void)
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{
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ulong now = READ_TIMER();
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if (lastdec >= now) {
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/* normal mode */
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timestamp += lastdec - now;
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} else {
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/* we have an overflow ... */
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timestamp += lastdec + timer_load_val - now;
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}
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lastdec = now;
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return timestamp;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= (timer_load_val * 100);
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tmo /= 1000;
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} else {
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tmo = usec * (timer_load_val * 100);
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tmo /= (1000*1000);
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}
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endtime = get_timer_masked () + tmo;
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do {
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ulong now = get_timer_masked ();
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diff = endtime - now;
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} while (diff >= 0);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk (void)
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{
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ulong tbclk;
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#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
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tbclk = timer_load_val * 100;
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#elif defined(CONFIG_SBC2410X) || \
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defined(CONFIG_SMDK2410) || \
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defined(CONFIG_VCMA9)
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tbclk = CFG_HZ;
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#else
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# error "tbclk not configured"
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#endif
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return tbclk;
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}
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/*
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* reset the cpu by setting up the watchdog timer and let him time out
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*/
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void reset_cpu (ulong ignored)
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{
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volatile S3C24X0_WATCHDOG * watchdog;
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#ifdef CONFIG_TRAB
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extern void disable_vfd (void);
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disable_vfd();
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#endif
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watchdog = S3C24X0_GetBase_WATCHDOG();
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/* Disable watchdog */
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watchdog->WTCON = 0x0000;
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/* Initialize watchdog timer count register */
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watchdog->WTCNT = 0x0001;
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/* Enable watchdog timer; assert reset at timer timeout */
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watchdog->WTCON = 0x0021;
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while(1); /* loop forever and wait for reset to happen */
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/*NOTREACHED*/
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}
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#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
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