mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
fb05f0b02b
As README.x86 already mentions, there are two SPI flashes mounted on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively. SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores the actual BIOS image which is U-Boot. Building a single image with both ME firmware and U-Boot does not make sense. This also describes the exact flash location where the u-boot.rom should be programmed in the documentation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
39 lines
944 B
Text
39 lines
944 B
Text
CONFIG_X86=y
|
|
CONFIG_SYS_TEXT_BASE=0xFFE00000
|
|
CONFIG_VENDOR_INTEL=y
|
|
CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
|
|
CONFIG_TARGET_COUGARCANYON2=y
|
|
# CONFIG_HAVE_INTEL_ME is not set
|
|
# CONFIG_ENABLE_MRC_CACHE is not set
|
|
CONFIG_USE_BOOTARGS=y
|
|
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
|
|
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
|
CONFIG_LAST_STAGE_INIT=y
|
|
CONFIG_HUSH_PARSER=y
|
|
# CONFIG_CMD_FLASH is not set
|
|
CONFIG_CMD_GPIO=y
|
|
CONFIG_CMD_PART=y
|
|
CONFIG_CMD_SF=y
|
|
CONFIG_CMD_SPI=y
|
|
CONFIG_CMD_USB=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
CONFIG_CMD_DHCP=y
|
|
# CONFIG_CMD_NFS is not set
|
|
CONFIG_CMD_PING=y
|
|
CONFIG_CMD_TIME=y
|
|
CONFIG_CMD_EXT2=y
|
|
CONFIG_CMD_EXT4=y
|
|
CONFIG_CMD_EXT4_WRITE=y
|
|
CONFIG_CMD_FAT=y
|
|
CONFIG_CMD_FS_GENERIC=y
|
|
CONFIG_MAC_PARTITION=y
|
|
CONFIG_ISO_PARTITION=y
|
|
CONFIG_EFI_PARTITION=y
|
|
CONFIG_REGMAP=y
|
|
CONFIG_SYSCON=y
|
|
CONFIG_SYS_NS16550=y
|
|
CONFIG_SPI=y
|
|
CONFIG_USB_STORAGE=y
|
|
CONFIG_USB_KEYBOARD=y
|
|
# CONFIG_VIDEO_VESA is not set
|