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a723074550
This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
20 lines
407 B
C
20 lines
407 B
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra20 clock control functions */
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#ifndef _TEGRA20_CLOCK_H
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#define _TEGRA20_CLOCK_H
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#include <asm/arch-tegra/clock.h>
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/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
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#define OSC_FREQ_SHIFT 30
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#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
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int tegra_plle_enable(void);
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#endif /* _TEGRA20_CLOCK_H */
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