mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
19a75b8cf8
The workaround for ARM errata 725233 had been lost since
commit 45bf05854b (armv7: adapt omap3 to the new cache
maintenance framework). Bring it back in order to avoid
very difficult to reproduce, but actually encountered in
the wild CPU deadlocks when running software rendered
X11 desktop on OMAP3530 hardware.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Migrate to Kconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
282 lines
7 KiB
C
282 lines
7 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _OMAP3_H_
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#define _OMAP3_H_
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#include <linux/sizes.h>
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/* Stuff on L3 Interconnect */
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#define SMX_APE_BASE 0x68000000
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/* GPMC */
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#define OMAP34XX_GPMC_BASE 0x6E000000
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/* SMS */
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#define OMAP34XX_SMS_BASE 0x6C000000
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/* SDRC */
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#define OMAP34XX_SDRC_BASE 0x6D000000
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now
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*/
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#define OMAP34XX_CORE_L4_IO_BASE 0x48000000
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#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000
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#define OMAP34XX_ID_L4_IO_BASE 0x4830A200
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#define OMAP34XX_L4_PER 0x49000000
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#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE
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/* DMA4/SDMA */
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#define OMAP34XX_DMA4_BASE 0x48056000
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/* CONTROL */
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#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000)
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#ifndef __ASSEMBLY__
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/* Signal Integrity Parameter Control Registers */
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struct control_prog_io {
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unsigned char res[0x408];
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unsigned int io2; /* 0x408 */
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unsigned char res2[0x38];
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unsigned int io0; /* 0x444 */
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unsigned int io1; /* 0x448 */
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};
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#endif /* __ASSEMBLY__ */
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/* Bit definition for CONTROL_PROG_IO1 */
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#define PRG_I2C2_PULLUPRESX 0x00000001
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/* Scratchpad memory */
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#define OMAP34XX_SCRATCHPAD (OMAP34XX_CTRL_BASE + 0x910)
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/* UART */
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#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
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#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
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#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
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#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
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/* General Purpose Timers */
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#define OMAP34XX_GPT1 0x48318000
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#define OMAP34XX_GPT2 0x49032000
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#define OMAP34XX_GPT3 0x49034000
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#define OMAP34XX_GPT4 0x49036000
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#define OMAP34XX_GPT5 0x49038000
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#define OMAP34XX_GPT6 0x4903A000
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#define OMAP34XX_GPT7 0x4903C000
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#define OMAP34XX_GPT8 0x4903E000
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#define OMAP34XX_GPT9 0x49040000
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#define OMAP34XX_GPT10 0x48086000
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#define OMAP34XX_GPT11 0x48088000
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#define OMAP34XX_GPT12 0x48304000
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/* WatchDog Timers (1 secure, 3 GP) */
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#define WD1_BASE 0x4830C000
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#define WD2_BASE 0x48314000
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#define WD3_BASE 0x49030000
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/* 32KTIMER */
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#define SYNC_32KTIMER_BASE 0x48320000
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#ifndef __ASSEMBLY__
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struct s32ktimer {
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unsigned char res[0x10];
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unsigned int s32k_cr; /* 0x10 */
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};
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#endif /* __ASSEMBLY__ */
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#ifndef __ASSEMBLY__
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struct gpio {
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unsigned char res1[0x34];
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unsigned int oe; /* 0x34 */
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unsigned int datain; /* 0x38 */
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unsigned char res2[0x54];
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unsigned int cleardataout; /* 0x90 */
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unsigned int setdataout; /* 0x94 */
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};
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#endif /* __ASSEMBLY__ */
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#define GPIO0 (0x1 << 0)
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#define GPIO1 (0x1 << 1)
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#define GPIO2 (0x1 << 2)
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#define GPIO3 (0x1 << 3)
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#define GPIO4 (0x1 << 4)
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#define GPIO5 (0x1 << 5)
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#define GPIO6 (0x1 << 6)
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#define GPIO7 (0x1 << 7)
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#define GPIO8 (0x1 << 8)
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#define GPIO9 (0x1 << 9)
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#define GPIO10 (0x1 << 10)
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#define GPIO11 (0x1 << 11)
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#define GPIO12 (0x1 << 12)
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#define GPIO13 (0x1 << 13)
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#define GPIO14 (0x1 << 14)
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#define GPIO15 (0x1 << 15)
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#define GPIO16 (0x1 << 16)
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#define GPIO17 (0x1 << 17)
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#define GPIO18 (0x1 << 18)
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#define GPIO19 (0x1 << 19)
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#define GPIO20 (0x1 << 20)
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#define GPIO21 (0x1 << 21)
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#define GPIO22 (0x1 << 22)
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#define GPIO23 (0x1 << 23)
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#define GPIO24 (0x1 << 24)
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#define GPIO25 (0x1 << 25)
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#define GPIO26 (0x1 << 26)
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#define GPIO27 (0x1 << 27)
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#define GPIO28 (0x1 << 28)
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#define GPIO29 (0x1 << 29)
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#define GPIO30 (0x1 << 30)
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#define GPIO31 (0x1 << 31)
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_OFFSET0 0x40000000
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#define SRAM_OFFSET1 0x00200000
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#define SRAM_OFFSET2 0x0000F800
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#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \
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SRAM_OFFSET2)
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#define SRAM_CLK_CODE (SRAM_VECT_CODE + 64)
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#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
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#define NON_SECURE_SRAM_END 0x40210000
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#define NON_SECURE_SRAM_IMG_END 0x4020F000
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#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
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#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
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/* scratch area - accessible on both EMU and GP */
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#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA NON_SECURE_SRAM_START
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#define DEBUG_LED1 149 /* gpio */
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#define DEBUG_LED2 150 /* gpio */
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#define XDR_POP 5 /* package on package part */
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#define SDR_DISCRETE 4 /* 128M memory SDR module */
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#define DDR_STACKED 3 /* stacked part on 2422 */
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#define DDR_COMBO 2 /* combo part on cpu daughter card */
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#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
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#define DDR_100 100 /* type found on most mem d-boards */
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#define DDR_111 111 /* some combo parts */
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#define DDR_133 133 /* most combo, some mem d-boards */
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#define DDR_165 165 /* future parts */
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#define CPU_3430 0x3430
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/*
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* 343x real hardware:
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* ES1 = rev 0
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*
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* ES2 onwards, the value maps to contents of IDCODE register [31:28].
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*
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* Note : CPU_3XX_ES20 is used in cache.S. Please review before changing.
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*/
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#define CPU_3XX_ES10 0
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#define CPU_3XX_ES20 1
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#define CPU_3XX_ES21 2
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#define CPU_3XX_ES30 3
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#define CPU_3XX_ES31 4
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#define CPU_3XX_ES312 7
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#define CPU_3XX_MAX_REV 8
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/*
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* 37xx real hardware:
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* ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
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*/
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#define CPU_37XX_ES10 0
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#define CPU_37XX_ES11 1
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#define CPU_37XX_ES12 2
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#define CPU_37XX_MAX_REV 3
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#define CPU_3XX_ID_SHIFT 28
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#define WIDTH_8BIT 0x0000
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#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */
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/*
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* Hawkeye values
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*/
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#define HAWKEYE_OMAP34XX 0xb7ae
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#define HAWKEYE_AM35XX 0xb868
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#define HAWKEYE_OMAP36XX 0xb891
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#define HAWKEYE_SHIFT 12
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/*
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* Define CPU families
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*/
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#define CPU_OMAP34XX 0x3400 /* OMAP34xx/OMAP35 devices */
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#define CPU_AM35XX 0x3500 /* AM35xx devices */
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#define CPU_OMAP36XX 0x3600 /* OMAP36xx devices */
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/*
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* Control status register values corresponding to cpu variants
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*/
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#define OMAP3503 0x5c00
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#define OMAP3515 0x1c00
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#define OMAP3525 0x4c00
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#define OMAP3530 0x0c00
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#define AM3505 0x5c00
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#define AM3517 0x1c00
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#define OMAP3730 0x0c00
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#define OMAP3725 0x4c00
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#define AM3715 0x1c00
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#define AM3703 0x5c00
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#define OMAP3730_1GHZ 0x0e00
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#define OMAP3725_1GHZ 0x4e00
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#define AM3715_1GHZ 0x1e00
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#define AM3703_1GHZ 0x5e00
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/*
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* ROM code API related flags
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*/
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#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
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#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR 2
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#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
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/*
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* EMU device PPA HAL related flags
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*/
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#define OMAP3_EMU_HAL_API_L2_INVAL 40
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#define OMAP3_EMU_HAL_API_WRITE_ACR 42
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#define OMAP3_EMU_HAL_START_HAL_CRITICAL 4
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/* ABB settings */
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#define OMAP_ABB_SETTLING_TIME 30
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#define OMAP_ABB_CLOCK_CYCLES 8
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/* ABB tranxdone mask */
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#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
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#define OMAP_REBOOT_REASON_OFFSET 0x04
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/* Boot parameters */
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#ifndef __ASSEMBLY__
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struct omap_boot_parameters {
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unsigned int boot_message;
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unsigned char boot_device;
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unsigned char reserved;
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unsigned char reset_reason;
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unsigned char ch_flags;
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unsigned int boot_device_descriptor;
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};
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int omap_reboot_mode(char *mode, unsigned int length);
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int omap_reboot_mode_clear(void);
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int omap_reboot_mode_store(char *mode);
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#endif
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#endif
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