mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 01:17:39 +00:00
a94a4071d4
Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
486 lines
11 KiB
C
486 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for TI AM335X based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <net.h>
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#include <serial.h>
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#include <asm/global_data.h>
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#include <linux/libfdt.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65910.h>
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#include <watchdog.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO that controls DIP switch and mPCIe slot */
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#define DIP_S1 44
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#define MPCIE_SW 100
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static int baltos_set_console(void)
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{
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int val, i, dips = 0;
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char buf[7];
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for (i = 0; i < 4; i++) {
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sprintf(buf, "dip_s%d", i + 1);
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if (gpio_request(DIP_S1 + i, buf)) {
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printf("failed to export GPIO %d\n", DIP_S1 + i);
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return 0;
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}
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if (gpio_direction_input(DIP_S1 + i)) {
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printf("failed to set GPIO %d direction\n", DIP_S1 + i);
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return 0;
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}
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val = gpio_get_value(DIP_S1 + i);
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dips |= val << i;
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}
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printf("DIPs: 0x%1x\n", (~dips) & 0xf);
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if ((dips & 0xf) == 0xe)
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env_set("console", "ttyUSB0,115200n8");
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return 0;
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}
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static int read_eeprom(BSP_VS_HWPARAM *header)
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{
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int rc;
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struct udevice *dev;
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struct udevice *bus;
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rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
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if (rc)
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return rc;
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/* Check if baseboard eeprom is available */
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if (dm_i2c_probe(bus, CONFIG_SYS_I2C_EEPROM_ADDR, 0, &dev)) {
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puts("Could not probe the EEPROM; something fundamentally "
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"wrong on the I2C bus.\n");
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return -ENODEV;
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}
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/* read the eeprom using i2c */
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if (dm_i2c_read(dev, 0, (uchar *)header,
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sizeof(BSP_VS_HWPARAM))) {
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puts("Could not read the EEPROM; something fundamentally"
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" wrong on the I2C bus.\n");
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return -EIO;
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}
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if (header->Magic != 0xDEADBEEF) {
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printf("Incorrect magic number (0x%x) in EEPROM\n",
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header->Magic);
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/* fill default values */
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header->SystemId = 211;
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header->MAC1[0] = 0x00;
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header->MAC1[1] = 0x00;
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header->MAC1[2] = 0x00;
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header->MAC1[3] = 0x00;
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header->MAC1[4] = 0x00;
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header->MAC1[5] = 0x01;
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header->MAC2[0] = 0x00;
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header->MAC2[1] = 0x00;
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header->MAC2[2] = 0x00;
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header->MAC2[3] = 0x00;
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header->MAC2[4] = 0x00;
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header->MAC2[5] = 0x02;
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header->MAC3[0] = 0x00;
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header->MAC3[1] = 0x00;
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header->MAC3[2] = 0x00;
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header->MAC3[3] = 0x00;
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header->MAC3[4] = 0x00;
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header->MAC3[5] = 0x03;
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}
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return 0;
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}
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
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static const struct ddr_data ddr3_baltos_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_baltos_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return (serial_tstc() && serial_getc() == 'c');
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}
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#endif
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr = {
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266, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_evm_sk = {
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303, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_baltos = {
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400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int sil_rev, mpu_vdd;
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int freq;
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enable_i2c1_pin_mux();
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i2c_set_bus_num(1);
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freq = am335x_get_efuse_mpu_max_freq(cdev);
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/*
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* The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
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* MPU frequencies we support we use a CORE voltage of
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* 1.1375V. For MPU voltage we need to switch based on
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* the frequency we are running at.
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*/
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if (power_tps65910_init(1))
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return;
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/*
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* Depending on MPU clock and PG we will need a different
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* VDD to drive at that speed.
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*/
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sil_rev = readl(&cdev->deviceid) >> 28;
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mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
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/* Tell the TPS65910 to use i2c */
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tps65910_set_i2c_control();
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/* First update MPU voltage. */
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if (tps65910_voltage_update(MPU, mpu_vdd))
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return;
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/* Second, update the CORE voltage. */
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if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
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return;
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writel(0x000010ff, PRM_DEVICE_INST + 4);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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enable_i2c1_pin_mux();
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i2c_set_bus_num(1);
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return &dpll_ddr_baltos;
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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const struct ctrl_ioregs ioregs_baltos = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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void sdram_init(void)
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{
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config_ddr(400, &ioregs_baltos,
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&ddr3_baltos_data,
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&ddr3_baltos_cmd_ctrl_data,
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&ddr3_baltos_emif_reg_data, 0);
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
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#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
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gpmc_init();
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#endif
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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int node, ret;
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unsigned char mac_addr[6];
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BSP_VS_HWPARAM header;
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/* get production data */
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if (read_eeprom(&header))
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return 0;
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/* setup MAC1 */
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mac_addr[0] = header.MAC1[0];
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mac_addr[1] = header.MAC1[1];
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mac_addr[2] = header.MAC1[2];
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mac_addr[3] = header.MAC1[3];
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mac_addr[4] = header.MAC1[4];
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mac_addr[5] = header.MAC1[5];
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node = fdt_path_offset(blob, "ethernet0");
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if (node < 0) {
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printf("no ethernet0 path offset\n");
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return -ENODEV;
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}
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ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
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if (ret) {
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printf("error setting mac-address property\n");
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return -ENODEV;
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}
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/* setup MAC2 */
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mac_addr[0] = header.MAC2[0];
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mac_addr[1] = header.MAC2[1];
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mac_addr[2] = header.MAC2[2];
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mac_addr[3] = header.MAC2[3];
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mac_addr[4] = header.MAC2[4];
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mac_addr[5] = header.MAC2[5];
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node = fdt_path_offset(blob, "ethernet1");
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if (node < 0) {
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printf("no ethernet1 path offset\n");
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return -ENODEV;
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}
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ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
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if (ret) {
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printf("error setting mac-address property\n");
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return -ENODEV;
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}
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printf("\nFDT was successfully setup\n");
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return 0;
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}
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static struct module_pin_mux pcie_sw_pin_mux[] = {
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{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
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{-1},
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};
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static struct module_pin_mux dip_pin_mux[] = {
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{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
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{OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
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{OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
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{OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
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{-1},
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};
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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BSP_VS_HWPARAM header;
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char model[4];
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/* get production data */
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if (read_eeprom(&header)) {
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strcpy(model, "211");
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} else {
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sprintf(model, "%d", header.SystemId);
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if (header.SystemId == 215) {
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configure_module_pin_mux(dip_pin_mux);
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baltos_set_console();
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}
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}
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/* turn power for the mPCIe slot */
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configure_module_pin_mux(pcie_sw_pin_mux);
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if (gpio_request(MPCIE_SW, "mpcie_sw")) {
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printf("failed to export GPIO %d\n", MPCIE_SW);
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return -ENODEV;
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}
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if (gpio_direction_output(MPCIE_SW, 1)) {
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printf("failed to set GPIO %d direction\n", MPCIE_SW);
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return -ENODEV;
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}
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env_set("board_name", model);
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#endif
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return 0;
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}
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#endif
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 7,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 2,
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.slave_data = cpsw_slaves,
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.active_slave = 1,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#endif
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#if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
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&& defined(CONFIG_SPL_BUILD)) || \
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((defined(CONFIG_DRIVER_TI_CPSW) || \
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defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
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!defined(CONFIG_SPL_BUILD))
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int board_eth_init(struct bd_info *bis)
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{
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int rv, n = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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/*
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* Note here that we're using CPSW1 since that has a 1Gbit PHY while
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* CSPW0 has a 100Mbit PHY.
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*
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* On product, CPSW1 maps to port labeled WAN.
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*/
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid1l);
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mac_hi = readl(&cdev->macid1h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
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if (!env_get("ethaddr")) {
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printf("<ethaddr> not set. Validating first E-fuse MAC\n");
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
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cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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#endif
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/*
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*
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* CPSW RGMII Internal Delay Mode is not supported in all PVT
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* operating points. So we must set the TX clock delay feature
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* in the AR8051 PHY. Since we only support a single ethernet
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* device in U-Boot, we only do this for the first instance.
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*/
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#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
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#define AR8051_PHY_DEBUG_DATA_REG 0x1e
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#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
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#define AR8051_RGMII_TX_CLK_DLY 0x100
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const char *devname;
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devname = miiphy_get_current_dev();
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miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
|
|
AR8051_DEBUG_RGMII_CLK_DLY_REG);
|
|
miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
|
|
AR8051_RGMII_TX_CLK_DLY);
|
|
#endif
|
|
return n;
|
|
}
|
|
#endif
|