mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
e3e01a6f94
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. This patch is based on the corresponding Linux v6.5 device tree (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
144 lines
2.4 KiB
Text
144 lines
2.4 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
/*
|
|
* Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
|
|
*
|
|
* Copyright (C) 2021 Renesas Electronics Corp.
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
|
|
|
/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
|
|
#define PMOD1_SER0 1
|
|
|
|
/ {
|
|
aliases {
|
|
serial1 = &scif2;
|
|
i2c3 = &i2c3;
|
|
};
|
|
|
|
osc1: cec-clock {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <12000000>;
|
|
};
|
|
|
|
hdmi-out {
|
|
compatible = "hdmi-connector";
|
|
type = "d";
|
|
|
|
port {
|
|
hdmi_con_out: endpoint {
|
|
remote-endpoint = <&adv7535_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&cpu_dai {
|
|
sound-dai = <&ssi0>;
|
|
};
|
|
|
|
&dsi {
|
|
status = "okay";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
dsi0_in: endpoint {
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
dsi0_out: endpoint {
|
|
data-lanes = <1 2 3 4>;
|
|
remote-endpoint = <&adv7535_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
adv7535: hdmi@3d {
|
|
compatible = "adi,adv7535";
|
|
reg = <0x3d>;
|
|
|
|
interrupt-parent = <&pinctrl>;
|
|
interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
|
|
clocks = <&osc1>;
|
|
clock-names = "cec";
|
|
avdd-supply = <®_1p8v>;
|
|
dvdd-supply = <®_1p8v>;
|
|
pvdd-supply = <®_1p8v>;
|
|
a2vdd-supply = <®_1p8v>;
|
|
v3p3-supply = <®_3p3v>;
|
|
v1p2-supply = <®_1p8v>;
|
|
|
|
adi,dsi-lanes = <4>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
adv7535_in: endpoint {
|
|
remote-endpoint = <&dsi0_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
adv7535_out: endpoint {
|
|
remote-endpoint = <&hdmi_con_out>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
pinctrl-0 = <&i2c3_pins>;
|
|
pinctrl-names = "default";
|
|
clock-frequency = <400000>;
|
|
|
|
status = "okay";
|
|
|
|
wm8978: codec@1a {
|
|
compatible = "wlf,wm8978";
|
|
#sound-dai-cells = <0>;
|
|
reg = <0x1a>;
|
|
};
|
|
};
|
|
|
|
/*
|
|
* To enable SCIF2 (SER0) on PMOD1 (CN7)
|
|
* SW1 should be at position 2->3 so that SER0_CTS# line is activated
|
|
* SW2 should be at position 2->3 so that SER0_TX line is activated
|
|
* SW3 should be at position 2->3 so that SER0_RX line is activated
|
|
* SW4 should be at position 2->3 so that SER0_RTS# line is activated
|
|
*/
|
|
#if PMOD1_SER0
|
|
&scif2 {
|
|
pinctrl-0 = <&scif2_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
uart-has-rtscts;
|
|
status = "okay";
|
|
};
|
|
#endif
|
|
|
|
&ssi0 {
|
|
pinctrl-0 = <&ssi0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&vccq_sdhi1 {
|
|
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
|
|
};
|