mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
93cac45c97
Move the crypto and sec_jr* nodes from board-specific u-boot.dtsi files into the common files. Additionally protect the nodes with ifdef CONFIG_FSL_CAAM as they don't serve any purpose if that is not enabled. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
191 lines
2.8 KiB
Text
191 lines
2.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
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bootph-pre-ram;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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bootph-pre-ram;
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};
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&eqos {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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ðphy0 {
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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&flexspi {
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&i2c1 {
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bootph-pre-ram;
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&pca6416 {
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compatible = "ti,tca6416";
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label = "exp4";
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};
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&pca6416_1 {
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compatible = "ti,tca6416";
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label = "exp4";
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};
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&pca6416_3 {
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compatible = "ti,tca6416";
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label = "exp2";
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};
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&pinctrl_i2c1 {
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bootph-pre-ram;
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};
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&pinctrl_pmic {
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bootph-pre-ram;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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u-boot,off-on-delay-us = <20000>;
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};
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&tpm {
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compatible = "tcg,tpm_tis-spi";
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};
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&uart2 {
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bootph-pre-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc2 {
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bootph-pre-ram;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usdhc3 {
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bootph-pre-ram;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
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};
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&usb3_0 {
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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};
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&usb3_1 {
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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};
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&usb_dwc3_0 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};
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&usb_dwc3_1 {
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compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
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assigned-clock-rates = <400000000>;
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};
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&usdhc1 {
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status = "disabled";
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};
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&wdog1 {
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bootph-pre-ram;
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};
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