mirror of
https://github.com/AsahiLinux/u-boot
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113e5dfcd7
Samsung SoC is supported the WIDE8, even if Controller version is v2.0. So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
88 lines
2.2 KiB
C
88 lines
2.2 KiB
C
/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/clk.h>
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static char *S5P_NAME = "SAMSUNG SDHCI";
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static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
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{
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unsigned long val, ctrl;
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/*
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* SELCLKPADDS[17:16]
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* 00 = 2mA
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* 01 = 4mA
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* 10 = 7mA
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* 11 = 9mA
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*/
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sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
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val = sdhci_readl(host, SDHCI_CONTROL2);
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val &= SDHCI_CTRL2_SELBASECLK_SHIFT;
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val |= SDHCI_CTRL2_ENSTAASYNCCLR |
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SDHCI_CTRL2_ENCMDCNFMSK |
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SDHCI_CTRL2_ENFBCLKRX |
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SDHCI_CTRL2_ENCLKOUTHOLD;
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sdhci_writel(host, val, SDHCI_CONTROL2);
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/*
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* FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
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* FCSel[1:0] : Rx Feedback Clock Delay Control
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* Inverter delay means10ns delay if SDCLK 50MHz setting
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* 01 = Delay1 (basic delay)
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* 11 = Delay2 (basic delay + 2ns)
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* 00 = Delay3 (inverter delay)
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* 10 = Delay4 (inverter delay + 2ns)
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*/
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val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
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sdhci_writel(host, val, SDHCI_CONTROL3);
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/*
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* SELBASECLK[5:4]
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* 00/01 = HCLK
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* 10 = EPLL
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* 11 = XTI or XEXTCLK
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*/
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ctrl = sdhci_readl(host, SDHCI_CONTROL2);
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ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
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ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
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sdhci_writel(host, ctrl, SDHCI_CONTROL2);
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}
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int s5p_sdhci_init(u32 regbase, int index, int bus_width)
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{
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struct sdhci_host *host = NULL;
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host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
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if (!host) {
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printf("sdhci__host malloc fail!\n");
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return 1;
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}
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host->name = S5P_NAME;
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host->ioaddr = (void *)regbase;
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host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
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SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
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host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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host->set_control_reg = &s5p_sdhci_set_control_reg;
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host->set_clock = set_mmc_clk;
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host->index = index;
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host->host_caps = MMC_MODE_HC;
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if (bus_width == 8)
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host->host_caps |= MMC_MODE_8BIT;
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return add_sdhci(host, 52000000, 400000);
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}
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