mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
179 lines
7 KiB
C
179 lines
7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _CLASS_CSR_H_
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#define _CLASS_CSR_H_
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/*
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* @file class_csr.h.
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* class_csr - block containing all the classifier control and status register.
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* Mapped on CBUS and accessible from all PE's and ARM.
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*/
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#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
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#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
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#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
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/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
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#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
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/* LMEM header size for the Classifier block.
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* Data in the LMEM is written from this offset.
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*/
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#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
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/* DDR header size for the Classifier block.
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* Data in the DDR is written from this offset.
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*/
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#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
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/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
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#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
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/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
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#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
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/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
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#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
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/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
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#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
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/*
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* @name Class PE memory access. Allows external PE's and HOST to
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* read/write PMEM/DMEM memory ranges for each classifier PE.
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*/
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#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
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/* Internal Memory Access Write Data [31:0] */
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#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
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/* Internal Memory Access Read Data [31:0] */
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#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
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#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
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#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
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#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
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#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
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#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
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#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
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#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
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#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
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#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
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#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
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#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
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#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
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#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
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/* bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR */
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#define CLASS_BUS_ACCESS_ADDR_MASK (0x0001FFFF)
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#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
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#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
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/*
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* (route_entry_size[9:0], route_hash_size[23:16]
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* (this is actually ln2(size)))
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*/
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#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
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#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
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#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
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#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
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#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
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#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
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#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
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#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
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#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
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#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
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#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
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#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
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/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
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#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000)
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#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
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#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
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#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
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#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
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#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
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#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
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#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
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#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
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#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
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#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
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#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
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#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
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#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
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#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
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#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
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#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
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#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
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#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
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#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
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#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
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#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
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#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
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#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
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#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
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#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
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#define CLASS_AXI_CTRL (CLASS_CSR_BASE_ADDR + 0x2d0)
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/* CLASS defines */
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#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
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#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
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#define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */
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/* Can be configured */
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#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
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/* Can be configured */
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#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
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/* Can be configured */
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#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
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#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR +\
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CLASS_PBUF_HEADER_OFFSET)
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#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR +\
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CLASS_PBUF_HEADER_OFFSET)
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#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR +\
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CLASS_PBUF_HEADER_OFFSET)
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#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR +\
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CLASS_PBUF_HEADER_OFFSET)
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#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) |\
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CLASS_PBUF0_BASE_ADDR)
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#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) |\
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CLASS_PBUF2_BASE_ADDR)
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#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16)\
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| CLASS_PBUF0_HEADER_BASE_ADDR)
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#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16)\
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| CLASS_PBUF2_HEADER_BASE_ADDR)
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#define CLASS_ROUTE_SIZE 128
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#define CLASS_ROUTE_HASH_BITS 20
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#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1)
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#define TWO_LEVEL_ROUTE BIT(0)
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#define PHYNO_IN_HASH BIT(1)
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#define HW_ROUTE_FETCH BIT(3)
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#define HW_BRIDGE_FETCH BIT(5)
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#define IP_ALIGNED BIT(6)
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#define ARC_HIT_CHECK_EN BIT(7)
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#define CLASS_TOE BIT(11)
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#define HASH_CRC_PORT BIT(12)
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#define HASH_CRC_IP BIT(13)
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#define HASH_CRC_PORT_IP GENMASK(13, 12)
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#define QB2BUS_LE BIT(15)
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#define TCP_CHKSUM_DROP BIT(0)
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#define UDP_CHKSUM_DROP BIT(1)
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#define IPV4_CHKSUM_DROP BIT(9)
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struct class_cfg {
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u32 route_table_baseaddr;
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u32 route_table_hash_bits;
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};
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#endif /* _CLASS_CSR_H_ */
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