mirror of
https://github.com/AsahiLinux/u-boot
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3ce1ef5b8f
Currently there are two targets for the i.MX6SX SabreSD board: mx6sxsabresd_defconfig and mx6sxsabresd_spl_defconfig. This brings additional maintainance effort without a clear advantage. Keep only the mx6sxsabresd_defconfig one and remove mx6sxsabresd_spl_defconfig to keep it simpler. Also remove the SPL related code from the board file. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
323 lines
9.2 KiB
C
323 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*/
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <env.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include "../common/pfuze.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
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#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_b_pad = {
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MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static iomux_v3_cfg_t const peri_3v3_pads[] = {
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MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const phy_control_pads[] = {
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/* 25MHz Ethernet PHY Clock */
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MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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/* ENET PHY Power */
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MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* AR8031 PHY Reset */
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MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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static int setup_fec(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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int reg, ret;
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/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
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ret = enable_fec_anatop_clock(0, ENET_125MHZ);
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if (ret)
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return ret;
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imx_iomux_v3_setup_multiple_pads(phy_control_pads,
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ARRAY_SIZE(phy_control_pads));
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/* Enable the ENET power, active low */
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gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
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gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
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/* Reset AR8031 PHY */
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gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
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gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
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mdelay(10);
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gpio_set_value(IMX_GPIO_NR(2, 7), 1);
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reg = readl(&anatop->pll_enet);
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reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
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writel(reg, &anatop->pll_enet);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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setup_fec();
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return cpu_eth_init(bis);
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}
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int power_init_board(void)
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{
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struct udevice *dev;
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unsigned int reg;
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int ret;
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dev = pfuze_common_init();
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if (!dev)
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return -ENODEV;
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ret = pfuze_mode_init(dev, APS_PFM);
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if (ret < 0)
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return ret;
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/* Enable power of VGEN5 3V3, needed for SD3 */
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reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
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reg &= ~LDO_VOL_MASK;
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reg |= (LDOB_3_30V | (1 << LDO_EN));
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pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/*
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* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
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* Phy control debug reg 0
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*/
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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/* rgmii tx clock delay enable */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
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imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
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ARRAY_SIZE(peri_3v3_pads));
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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#ifdef CONFIG_FSL_QSPI
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int board_qspi_init(void)
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{
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/* Set the clock */
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enable_qspi_clk(1);
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return 0;
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}
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#endif
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#ifdef CONFIG_VIDEO_MXS
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static iomux_v3_cfg_t const lcd_pads[] = {
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MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* Use GPIO for Brightness adjustment, duty cycle = period */
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MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static int setup_lcd(void)
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{
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enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
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imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
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/* Reset the LCD */
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gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
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gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
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udelay(500);
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gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
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/* Set Brightness to high */
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gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
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gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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/*
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* Because kernel set WDOG_B mux before pad with the common pinctrl
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* framwork now and wdog reset will be triggered once set WDOG_B mux
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* with default pad setting, we set pad setting here to workaround this.
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* Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
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* as GPIO mux firstly here to workaround it.
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*/
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imx_iomux_v3_setup_pad(wdog_b_pad);
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/* Active high for ncp692 */
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gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
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gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
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#ifdef CONFIG_FSL_QSPI
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board_qspi_init();
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#endif
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#ifdef CONFIG_VIDEO_MXS
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setup_lcd();
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#endif
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return 0;
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}
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static bool is_reva(void)
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{
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return (nxp_board_rev() == 1);
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (is_reva())
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env_set("board_rev", "REVA");
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#endif
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
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return 0;
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}
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