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https://github.com/AsahiLinux/u-boot
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b52a199e32
Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
273 lines
7.5 KiB
C
273 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <spl.h>
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#include <spl_gpio.h>
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#include <syscon.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/gpio.h>
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#include <asm/arch-rockchip/grf_rk3399.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_EMMCCORE_CON11 0xff77f02c
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#define GRF_BASE 0xff770000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000",
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[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000",
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};
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static struct mm_region rk3399_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xf8000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf8000000UL,
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.phys = 0xf8000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3399_mem_map;
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#ifdef CONFIG_SPL_BUILD
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#define TIMER_END_COUNT_L 0x00
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#define TIMER_END_COUNT_H 0x04
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#define TIMER_INIT_COUNT_L 0x10
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#define TIMER_INIT_COUNT_H 0x14
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#define TIMER_CONTROL_REG 0x1c
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#define TIMER_EN 0x1
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#define TIMER_FMODE BIT(0)
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#define TIMER_RMODE BIT(1)
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
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if (reg & TIMER_EN)
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return;
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_L);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_END_COUNT_H);
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_L);
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_INIT_COUNT_H);
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writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + \
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TIMER_CONTROL_REG);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct rk3399_pmusgrf_regs *sgrf;
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struct rk3399_grf_regs *grf;
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/*
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* Disable DDR and SRAM security regions.
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*
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* As we are entered from the BootROM, the region from
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* 0x0 through 0xfffff (i.e. the first MB of memory) will
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* be protected. This will cause issues with the DW_MMC
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* driver, which tries to DMA from/to the stack (likely)
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* located in this range.
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*/
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sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
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rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
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rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
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/* eMMC clock generator: disable the clock multipilier */
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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rk_clrreg(&grf->emmccore_con[11], 0x0ff);
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#endif
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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#define GRF_BASE 0xff770000
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#define GPIO0_BASE 0xff720000
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#define PMUGRF_BASE 0xff320000
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struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
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#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
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struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
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#endif
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
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/* Enable early UART0 on the RK3399 */
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rk_clrsetreg(&grf->gpio2c_iomux,
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GRF_GPIO2C0_SEL_MASK,
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GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2c_iomux,
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GRF_GPIO2C1_SEL_MASK,
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GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1B0000)
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/* Enable early UART3 on the RK3399 */
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rk_clrsetreg(&grf->gpio3b_iomux,
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GRF_GPIO3B6_SEL_MASK,
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GRF_UART3_SIN << GRF_GPIO3B6_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio3b_iomux,
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GRF_GPIO3B7_SEL_MASK,
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GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT);
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#else
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# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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rk_setreg(&grf->io_vsel, 1 << 0);
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/*
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* Let's enable these power rails here, we are already running the SPI
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* Flash based code.
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*/
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spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */
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spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL);
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spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */
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spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
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#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
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/* Enable early UART2 channel C on the RK3399 */
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rk_clrsetreg(&grf->gpio4c_iomux,
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GRF_GPIO4C3_SEL_MASK,
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GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio4c_iomux,
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GRF_GPIO4C4_SEL_MASK,
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GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
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/* Set channel C as UART2 input */
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rk_clrsetreg(&grf->soc_con7,
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GRF_UART_DBG_SEL_MASK,
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GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
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#endif
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}
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#endif
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#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
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const char *spl_decode_boot_device(u32 boot_device)
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{
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int i;
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static const struct {
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u32 boot_device;
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const char *ofpath;
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} spl_boot_devices_tbl[] = {
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{ BOOT_DEVICE_MMC1, "/dwmmc@fe320000" },
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{ BOOT_DEVICE_MMC2, "/sdhci@fe330000" },
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{ BOOT_DEVICE_SPI, "/spi@ff1d0000" },
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};
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for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
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if (spl_boot_devices_tbl[i].boot_device == boot_device)
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return spl_boot_devices_tbl[i].ofpath;
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return NULL;
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}
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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void *blob = spl_image->fdt_addr;
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const char *boot_ofpath;
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int chosen;
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/*
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* Inject the ofpath of the device the full U-Boot (or Linux in
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* Falcon-mode) was booted from into the FDT, if a FDT has been
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* loaded at the same time.
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*/
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if (!blob)
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return;
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boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
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if (!boot_ofpath) {
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pr_err("%s: could not map boot_device to ofpath\n", __func__);
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return;
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}
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chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
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if (chosen < 0) {
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pr_err("%s: could not find/create '/chosen'\n", __func__);
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return;
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}
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fdt_setprop_string(blob, chosen,
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"u-boot,spl-boot-device", boot_ofpath);
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}
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#if defined(SPL_GPIO_SUPPORT)
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static void rk3399_force_power_on_reset(void)
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{
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ofnode node;
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struct gpio_desc sysreset_gpio;
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debug("%s: trying to force a power-on reset\n", __func__);
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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debug("%s: no /config node?\n", __func__);
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return;
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}
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if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0,
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&sysreset_gpio, GPIOD_IS_OUT)) {
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debug("%s: could not find a /config/sysreset-gpio\n", __func__);
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return;
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}
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dm_gpio_set_value(&sysreset_gpio, 1);
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}
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#endif
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void spl_board_init(void)
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{
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#if defined(SPL_GPIO_SUPPORT)
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struct rockchip_cru *cru = rockchip_get_cru();
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/*
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* The RK3399 resets only 'almost all logic' (see also in the TRM
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* "3.9.4 Global software reset"), when issuing a software reset.
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* This may cause issues during boot-up for some configurations of
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* the application software stack.
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*
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* To work around this, we test whether the last reset reason was
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* a power-on reset and (if not) issue an overtemp-reset to reset
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* the entire module.
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*
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* While this was previously fixed by modifying the various places
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* that could generate a software reset (e.g. U-Boot's sysreset
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* driver, the ATF or Linux), we now have it here to ensure that
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* we no longer have to track this through the various components.
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*/
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if (cru->glb_rst_st != 0)
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rk3399_force_power_on_reset();
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#endif
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#if defined(SPL_DM_REGULATOR)
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/*
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* Turning the eMMC and SPI back on (if disabled via the Qseven
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* BIOS_ENABLE) signal is done through a always-on regulator).
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*/
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if (regulators_enable_boot_on(false))
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debug("%s: Cannot enable boot on regulator\n", __func__);
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#endif
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}
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#endif
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