mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
200 lines
5.5 KiB
C
200 lines
5.5 KiB
C
/*
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* linux/drivers/mmc/mmc_pxa.h
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*
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* Author: Vladimir Shebordaev, Igor Oblakov
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* Copyright: MontaVista Software Inc.
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*
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* $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __MMC_PXA_P_H__
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#define __MMC_PXA_P_H__
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/* PXA-250 MMC controller registers */
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/* MMC_STRPCL */
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#define MMC_STRPCL_STOP_CLK (0x0001UL)
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#define MMC_STRPCL_START_CLK (0x0002UL)
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/* MMC_STAT */
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#define MMC_STAT_END_CMD_RES (0x0001UL << 13)
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#define MMC_STAT_PRG_DONE (0x0001UL << 12)
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#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
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#define MMC_STAT_CLK_EN (0x0001UL << 8)
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#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
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#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
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#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
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#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4)
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#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
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#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
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#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
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#define MMC_STAT_READ_TIME_OUT (0x0001UL)
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#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
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|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
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|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
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/* MMC_CLKRT */
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#define MMC_CLKRT_20MHZ (0x0000UL)
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#define MMC_CLKRT_10MHZ (0x0001UL)
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#define MMC_CLKRT_5MHZ (0x0002UL)
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#define MMC_CLKRT_2_5MHZ (0x0003UL)
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#define MMC_CLKRT_1_25MHZ (0x0004UL)
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#define MMC_CLKRT_0_625MHZ (0x0005UL)
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#define MMC_CLKRT_0_3125MHZ (0x0006UL)
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/* MMC_SPI */
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#define MMC_SPI_DISABLE (0x00UL)
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#define MMC_SPI_EN (0x01UL)
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#define MMC_SPI_CS_EN (0x01UL << 2)
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#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
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#define MMC_SPI_CRC_ON (0x01UL << 1)
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/* MMC_CMDAT */
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#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
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#define MMC_CMDAT_INIT (0x0001UL << 6)
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#define MMC_CMDAT_BUSY (0x0001UL << 5)
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#define MMC_CMDAT_STREAM (0x0001UL << 4)
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#define MMC_CMDAT_BLOCK (0x0000UL << 4)
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#define MMC_CMDAT_WRITE (0x0001UL << 3)
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#define MMC_CMDAT_READ (0x0000UL << 3)
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#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
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#define MMC_CMDAT_R1 (0x0001UL)
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#define MMC_CMDAT_R2 (0x0002UL)
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#define MMC_CMDAT_R3 (0x0003UL)
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/* MMC_RESTO */
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#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
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/* MMC_RDTO */
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#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
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/* MMC_BLKLEN */
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#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
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/* MMC_PRTBUF */
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#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
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#define MMC_PRTBUF_BUF_FULL (0x00UL )
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/* MMC_I_MASK */
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#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
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#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
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#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
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#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
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#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
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#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
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#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
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#define MMC_I_MASK_ALL (0x07fUL)
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/* MMC_I_REG */
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#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
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#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
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#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
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#define MMC_I_REG_STOP_CMD (0x01UL << 3)
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#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
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#define MMC_I_REG_PRG_DONE (0x01UL << 1)
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#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
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#define MMC_I_REG_ALL (0x007fUL)
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/* MMC_CMD */
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#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
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#define CMD(x) (x)
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#define MMC_DEFAULT_RCA 1
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#define MMC_BLOCK_SIZE 512
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#define MMC_CMD_RESET 0
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#define MMC_CMD_SEND_OP_COND 1
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#define MMC_CMD_ALL_SEND_CID 2
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#define MMC_CMD_SET_RCA 3
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#define MMC_CMD_SEND_CSD 9
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#define MMC_CMD_SEND_CID 10
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#define MMC_CMD_SEND_STATUS 13
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#define MMC_CMD_SET_BLOCKLEN 16
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#define MMC_CMD_READ_BLOCK 17
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#define MMC_CMD_RD_BLK_MULTI 18
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#define MMC_CMD_WRITE_BLOCK 24
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#define MMC_MAX_BLOCK_SIZE 512
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#define MMC_R1_IDLE_STATE 0x01
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#define MMC_R1_ERASE_STATE 0x02
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#define MMC_R1_ILLEGAL_CMD 0x04
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#define MMC_R1_COM_CRC_ERR 0x08
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#define MMC_R1_ERASE_SEQ_ERR 0x01
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#define MMC_R1_ADDR_ERR 0x02
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#define MMC_R1_PARAM_ERR 0x04
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#define MMC_R1B_WP_ERASE_SKIP 0x0002
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#define MMC_R1B_ERR 0x0004
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#define MMC_R1B_CC_ERR 0x0008
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#define MMC_R1B_CARD_ECC_ERR 0x0010
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#define MMC_R1B_WP_VIOLATION 0x0020
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#define MMC_R1B_ERASE_PARAM 0x0040
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#define MMC_R1B_OOR 0x0080
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#define MMC_R1B_IDLE_STATE 0x0100
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#define MMC_R1B_ERASE_RESET 0x0200
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#define MMC_R1B_ILLEGAL_CMD 0x0400
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#define MMC_R1B_COM_CRC_ERR 0x0800
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#define MMC_R1B_ERASE_SEQ_ERR 0x1000
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#define MMC_R1B_ADDR_ERR 0x2000
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#define MMC_R1B_PARAM_ERR 0x4000
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typedef struct mmc_cid
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{
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/* FIXME: BYTE_ORDER */
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uchar year:4,
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month:4;
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uchar sn[3];
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uchar fwrev:4,
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hwrev:4;
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uchar name[6];
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uchar id[3];
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} mmc_cid_t;
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typedef struct mmc_csd
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{
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uchar ecc:2,
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file_format:2,
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tmp_write_protect:1,
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perm_write_protect:1,
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copy:1,
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file_format_grp:1;
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uint64_t content_prot_app:1,
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rsvd3:4,
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write_bl_partial:1,
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write_bl_len:4,
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r2w_factor:3,
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default_ecc:2,
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wp_grp_enable:1,
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wp_grp_size:5,
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erase_grp_mult:5,
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erase_grp_size:5,
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c_size_mult1:3,
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vdd_w_curr_max:3,
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vdd_w_curr_min:3,
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vdd_r_curr_max:3,
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vdd_r_curr_min:3,
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c_size:12,
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rsvd2:2,
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dsr_imp:1,
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read_blk_misalign:1,
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write_blk_misalign:1,
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read_bl_partial:1;
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ushort read_bl_len:4,
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ccc:12;
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uchar tran_speed;
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uchar nsac;
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uchar taac;
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uchar rsvd1:2,
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spec_vers:4,
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csd_structure:2;
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} mmc_csd_t;
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#endif /* __MMC_PXA_P_H__ */
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