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https://github.com/AsahiLinux/u-boot
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98250e8e17
* prepare joining at91 and at91rm9200 * add modified copy of soc files to cpu/arm920t/at91 to make possible to compile at91rm9200 boards in at91 tree instead of at91rm9200 * add header files with c structure defs for AT91 MC, ST and TC * the new cpu files are using at91 c structure soc access * please read README.soc-at91 for details Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
163 lines
3.5 KiB
C
163 lines
3.5 KiB
C
/*
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* (C) Copyright 2002
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* Lineo, Inc. <www.lineo.com>
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* Bernhard Kuhn <bkuhn@lineo.com>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <asm/arch/at91_tc.h>
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#include <asm/arch/at91_pmc.h>
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/* the number of clocks per CONFIG_SYS_HZ */
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#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
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static u32 timestamp;
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static u32 lastinc;
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int timer_init(void)
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{
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at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* enables TC1.0 clock */
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writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */
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writel(0, &tc->bcr);
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writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
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AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
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writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
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/* set to MCLK/2 and restart the timer
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when the value in TC_RC is reached */
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writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
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writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
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writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
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writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
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lastinc = 0;
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timestamp = 0;
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return 0;
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}
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/*
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* timer without interrupts
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*/
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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void __udelay(unsigned long usec)
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{
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udelay_masked(usec);
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}
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void reset_timer_masked(void)
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{
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/* reset time */
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at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
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lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
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timestamp = 0;
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}
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ulong get_timer_raw(void)
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{
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at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
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u32 now;
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now = readl(&tc->tc[0].cv) & 0x0000ffff;
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if (now >= lastinc) {
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/* normal mode */
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timestamp += now - lastinc;
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} else {
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/* we have an overflow ... */
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timestamp += now + TIMER_LOAD_VAL - lastinc;
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}
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lastinc = now;
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return timestamp;
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}
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ulong get_timer_masked(void)
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{
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return get_timer_raw()/TIMER_LOAD_VAL;
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}
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void udelay_masked(unsigned long usec)
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{
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u32 tmo;
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u32 endtime;
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signed long diff;
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tmo = CONFIG_SYS_HZ_CLOCK / 1000;
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tmo *= usec;
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tmo /= 1000;
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endtime = get_timer_raw() + tmo;
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do {
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u32 now = get_timer_raw();
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diff = endtime - now;
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} while (diff >= 0);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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