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Sricharan R f9b814a8e9 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ 
The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
..
asm ARM: DRA7xx: Correct the SYS_CLK to 20MHZ 2013-06-10 08:43:10 -04:00