mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/*
|
|
* Bluestone board support
|
|
*
|
|
* Copyright (c) 2010, Applied Micro Circuits Corporation
|
|
* Author: Tirumala R Marri <tmarri@apm.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/apm821xx.h>
|
|
#include <libfdt.h>
|
|
#include <fdt_support.h>
|
|
#include <i2c.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/io.h>
|
|
#include <asm/mmu.h>
|
|
#include <asm/ppc4xx-gpio.h>
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
/*
|
|
* Setup the interrupt controller polarities, triggers, etc.
|
|
*/
|
|
mtdcr(UIC0SR, 0xffffffff); /* clear all */
|
|
mtdcr(UIC0ER, 0x00000000); /* disable all */
|
|
mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
|
|
mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
|
|
mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
|
|
mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
|
|
mtdcr(UIC0SR, 0xffffffff); /* clear all */
|
|
|
|
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
|
mtdcr(UIC1ER, 0x00000000); /* disable all */
|
|
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
|
|
mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
|
|
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
|
|
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
|
|
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
|
|
|
mtdcr(UIC2SR, 0xffffffff); /* clear all */
|
|
mtdcr(UIC2ER, 0x00000000); /* disable all */
|
|
mtdcr(UIC2CR, 0x00000000); /* all non-critical */
|
|
mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
|
|
mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
|
|
mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
|
|
mtdcr(UIC2SR, 0xffffffff); /* clear all */
|
|
|
|
mtdcr(UIC3SR, 0xffffffff); /* clear all */
|
|
mtdcr(UIC3ER, 0x00000000); /* disable all */
|
|
mtdcr(UIC3CR, 0x00000000); /* all non-critical */
|
|
mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
|
|
mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
|
|
mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
|
|
mtdcr(UIC3SR, 0xffffffff); /* clear all */
|
|
|
|
/*
|
|
* Configure PFC (Pin Function Control) registers
|
|
* UART0: 2 pins
|
|
*/
|
|
mtsdr(SDR0_PFC1, 0x0000000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
char buf[64];
|
|
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
|
|
puts("Board: Bluestone Evaluation Board");
|
|
|
|
if (i > 0) {
|
|
puts(", serial# ");
|
|
puts(buf);
|
|
}
|
|
putc('\n');
|
|
|
|
return 0;
|
|
}
|
|
|
|
int misc_init_r(void)
|
|
{
|
|
u32 sdr0_srst1 = 0;
|
|
|
|
/* Setup PLB4-AHB bridge based on the system address map */
|
|
mtdcr(AHB_TOP, 0x8000004B);
|
|
mtdcr(AHB_BOT, 0x8000004B);
|
|
|
|
/*
|
|
* The AHB Bridge core is held in reset after power-on or reset
|
|
* so enable it now
|
|
*/
|
|
mfsdr(SDR0_SRST1, sdr0_srst1);
|
|
sdr0_srst1 &= ~SDR0_SRST1_AHB;
|
|
mtsdr(SDR0_SRST1, sdr0_srst1);
|
|
|
|
return 0;
|
|
}
|