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https://github.com/AsahiLinux/u-boot
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c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
165 lines
6.7 KiB
C
165 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* ti816x_emif4.c
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*
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* TI816x emif4 configuration file
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*
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* Copyright (C) 2017, Konsulko Group
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <linux/delay.h>
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/*********************************************************************
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* Init DDR3 on TI816X EVM
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*********************************************************************/
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static void ddr_init_settings(const struct cmd_control *ctrl, int emif)
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{
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/*
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* setup use_rank_delays to 1. This is only necessary when
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* multiple ranks are in use. Though the EVM does not have
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* multiple ranks, this is a good value to set.
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*/
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writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS
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writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS
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writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS
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writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS
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config_cmd_ctrl(ctrl, emif);
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/* for ddr3 this needs to be set to 1 */
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writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */
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writel(0x1, DDRPHY_CONFIG_BASE + 0x104);
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writel(0x1, DDRPHY_CONFIG_BASE + 0x19C);
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writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8);
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writel(0x1, DDRPHY_CONFIG_BASE + 0x240);
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writel(0x1, DDRPHY_CONFIG_BASE + 0x24C);
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writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4);
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writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0);
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/*
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* This represents the initial value for the leveling process. The
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* value is a ratio - so 0x100 represents one cycle. The real delay
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* is determined through the leveling process.
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*
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* During the leveling process, 0x20 is subtracted from the value, so
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* we have added that to the value we want to set. We also set the
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* values such that byte3 completes leveling after byte2 and byte1
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* after byte0.
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*/
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x100);
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4);
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x248);
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writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */
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writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC);
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writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */
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writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */
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writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */
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writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */
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writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */
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writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */
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writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */
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}
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static void ddr3_sw_levelling(const struct ddr_data *data, int emif)
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{
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/* Set the correct value to DDR_VTP_CTRL_0 */
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writel(0x6, (DDRPHY_CONFIG_BASE + 0x358));
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writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108));
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writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC));
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writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250));
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writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4));
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writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC));
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writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180));
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writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224));
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writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8));
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writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120));
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writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4));
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writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268));
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writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C));
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writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8));
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writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C));
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writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210));
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writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4));
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}
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static struct dmm_lisa_map_regs *hw_lisa_map_regs =
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(struct dmm_lisa_map_regs *)DMM_BASE;
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#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420)
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void config_dmm(const struct dmm_lisa_map_regs *regs)
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{
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
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writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
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writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
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writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
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writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
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writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
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/* Enable Tiled Access */
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writel(0x80000000, DMM_PAT_BASE_ADDR);
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}
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void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
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const struct emif_regs *regs,
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const struct dmm_lisa_map_regs *lisa_regs, int nrs)
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{
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int i;
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enable_emif_clocks();
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for (i = 0; i < nrs; i++)
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ddr_init_settings(ctrl, i);
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enable_dmm_clocks();
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/* Program the DMM to for non-interleaved configuration */
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config_dmm(lisa_regs);
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/* Program EMIF CFG Registers */
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for (i = 0; i < nrs; i++) {
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set_sdram_timings(regs, i);
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config_sdram(regs, i);
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}
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udelay(1000);
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for (i = 0; i < nrs; i++)
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ddr3_sw_levelling(data, i);
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udelay(50000); /* Some delay needed */
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}
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