mirror of
https://github.com/AsahiLinux/u-boot
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fd4dc09a4c
MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.
Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)
MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board
for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board.
Linux dts commit details:
commit <f838dae7afd0> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1
MicroDev 2.0 board")
Add support for it.
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
118 lines
2 KiB
Text
118 lines
2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
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* Copyright (c) 2020 Amarula Solutions(India)
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-u-boot.dtsi"
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#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
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&vin {
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u-boot,dm-pre-reloc;
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};
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&vddcore {
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u-boot,dm-pre-reloc;
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};
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&vdd {
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u-boot,dm-pre-reloc;
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};
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&vddq_ddr {
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u-boot,dm-pre-reloc;
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};
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&rcc {
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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frac = < 0x1a04 >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = < 3 98 5 7 7 PQR(1,1,1) >;
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u-boot,dm-pre-reloc;
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};
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};
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