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166097e877
Add a clock driver for Exynos7420 SoC. There are about 25 clock controller blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks are added in this initial version of the driver. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
26 lines
854 B
Text
26 lines
854 B
Text
menu "Clock"
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config CLK
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bool "Enable clock driver support"
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depends on DM
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help
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This allows drivers to be provided for clock generators, including
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oscillators and PLLs. Devices can use a common clock API to request
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a particular clock rate and check on available clocks. Clocks can
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feed into other clocks in a tree structure, with multiplexers to
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choose the source for each clock.
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config SPL_CLK
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bool "Enable clock support in SPL"
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depends on CLK
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help
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The clock subsystem adds a small amount of overhead to the image.
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If this is acceptable and you have a need to use clock drivers in
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SPL, enable this option. It might provide a cleaner interface to
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setting up clocks within SPL, and allows the same drivers to be
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used as U-Boot proper.
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/exynos/Kconfig"
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endmenu
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