mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 17:58:23 +00:00
f9147d636c
This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
511 lines
17 KiB
C
511 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017, 2019-2021 NXP
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* Copyright 2015 Freescale Semiconductor
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*/
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#ifndef __LS2_RDB_H
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#define __LS2_RDB_H
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#include "ls2080a_common.h"
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#ifdef CONFIG_FSL_QSPI
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#ifdef CONFIG_TARGET_LS2081ARDB
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#define CONFIG_QIXIS_I2C_ACCESS
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#endif
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#endif
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#define I2C_MUX_CH_VOL_MONITOR 0xa
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#define I2C_VOL_MONITOR_ADDR 0x38
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/* step the IR regulator in 5mV increments */
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#define IR_VDD_STEP_DOWN 5
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#define IR_VDD_STEP_UP 5
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/* The lowest and highest voltage allowed for LS2080ARDB */
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#define VDD_MV_MIN 819
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#define VDD_MV_MAX 1212
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#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS3 0x53
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#define SPD_EEPROM_ADDRESS4 0x54
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#define SPD_EEPROM_ADDRESS5 0x55
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#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
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#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 2
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
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#endif
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/* SATA */
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#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
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#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
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#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
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#define CONFIG_SYS_NOR0_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR0_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) |\
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWP(0x1c))
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#define CONFIG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#ifdef CONFIG_MTD_NOR_FLASH
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
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CONFIG_SYS_FLASH_BASE + 0x40000000}
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#endif
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#define CONFIG_SYS_NAND_MAX_ECCPOS 256
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
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| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
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| CSOR_NAND_PB(128)) /* Pages Per Block 128*/
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/* ONFI NAND Flash mode0 Timing Params */
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
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FTIM0_NAND_TWP(0x30) | \
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FTIM0_NAND_TWCHT(0x0e) | \
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FTIM0_NAND_TWH(0x14))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
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FTIM1_NAND_TWBE(0xab) | \
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FTIM1_NAND_TRR(0x1c) | \
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FTIM1_NAND_TRP(0x30))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
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FTIM2_NAND_TREH(0x14) | \
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FTIM2_NAND_TWHRE(0x3c))
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#define CONFIG_SYS_NAND_FTIM3 0x0
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_FSL_QIXIS /* use common QIXIS code */
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#define QIXIS_LBMAP_SWITCH 0x06
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x04
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#define QIXIS_LBMAP_NAND 0x09
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RST_CTL_RESET_EN 0x30
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_RCW_SRC_NAND 0x119
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#define QIXIS_RST_FORCE_MEM 0x01
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#define CONFIG_SYS_CSPR3_EXT (0x0)
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#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
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#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
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/* QIXIS Timing parameters for IFC CS3 */
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#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0x3E))
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#define CONFIG_SYS_CS3_FTIM3 0x0
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#if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SPL_PAD_TO 0x80000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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/* Debug Server firmware */
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#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
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#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
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#endif
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
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#ifdef CONFIG_TARGET_LS2081ARDB
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#define CONFIG_FSL_QIXIS /* use common QIXIS code */
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#define QIXIS_QMAP_MASK 0x07
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#define QIXIS_QMAP_SHIFT 5
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_QSPI 0x00
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#define QIXIS_RCW_SRC_QSPI 0x62
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#define QIXIS_LBMAP_ALTBANK 0x20
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_RST_CTL_RESET_EN 0x30
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#endif
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/*
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* I2C
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*/
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#ifdef CONFIG_TARGET_LS2081ARDB
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#endif
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#define I2C_MUX_PCA_ADDR 0x75
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#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
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/* I2C bus multiplexer */
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#define I2C_MUX_CH_DEFAULT 0x8
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/* SPI */
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/*
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* RTC configuration
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*/
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#define RTC
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#ifdef CONFIG_TARGET_LS2081ARDB
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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#else
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#define CONFIG_RTC_DS3231 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#endif
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/* EEPROM */
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_FSL_MEMAC
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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#define BOOT_TARGET_DEVICES(func) \
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func(USB, usb, 0) \
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func(MMC, mmc, 0) \
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func(SCSI, scsi, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#ifdef CONFIG_TFABOOT
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#define QSPI_MC_INIT_CMD \
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"sf probe 0:0; " \
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"sf read 0x80640000 0x640000 0x80000; " \
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"env exists secureboot && " \
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"esbc_validate 0x80640000 && " \
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"esbc_validate 0x80680000; " \
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"sf read 0x80a00000 0xa00000 0x200000; " \
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"sf read 0x80e00000 0xe00000 0x100000; " \
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"fsl_mc start mc 0x80a00000 0x80e00000 \0"
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#define SD_MC_INIT_CMD \
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"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
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"mmc read 0x80e00000 0x7000 0x800;" \
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"env exists secureboot && " \
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"mmc read 0x80640000 0x3200 0x20 && " \
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"mmc read 0x80680000 0x3400 0x20 && " \
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"esbc_validate 0x80640000 && " \
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"esbc_validate 0x80680000 ;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0"
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#define IFC_MC_INIT_CMD \
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"env exists secureboot && " \
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"esbc_validate 0x580640000 && " \
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"esbc_validate 0x580680000; " \
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"fsl_mc start mc 0x580a00000 0x580e00000 \0"
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#else
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#ifdef CONFIG_QSPI_BOOT
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#define MC_INIT_CMD \
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"mcinitcmd=sf probe 0:0; " \
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"sf read 0x80640000 0x640000 0x80000; " \
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"env exists secureboot && " \
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"esbc_validate 0x80640000 && " \
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"esbc_validate 0x80680000; " \
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"sf read 0x80a00000 0xa00000 0x200000; " \
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"sf read 0x80e00000 0xe00000 0x100000; " \
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"fsl_mc start mc 0x80a00000 0x80e00000 \0"
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#elif defined(CONFIG_SD_BOOT)
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#define MC_INIT_CMD \
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"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
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"mmc read 0x80e00000 0x7000 0x800;" \
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"env exists secureboot && " \
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"mmc read 0x80640000 0x3200 0x20 && " \
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"mmc read 0x80680000 0x3400 0x20 && " \
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"esbc_validate 0x80640000 && " \
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"esbc_validate 0x80680000 ;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0" \
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"mcmemsize=0x70000000\0"
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#else
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#define MC_INIT_CMD \
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"mcinitcmd=env exists secureboot && " \
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"esbc_validate 0x580640000 && " \
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"esbc_validate 0x580680000; " \
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"fsl_mc start mc 0x580a00000 0x580e00000 \0"
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#endif
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#endif
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/* Initial environment variables */
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#ifdef CONFIG_TFABOOT
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"fdt_addr=0x64f00000\0" \
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"kernel_addr=0x581000000\0" \
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"kernel_start=0x1000000\0" \
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"kernelheader_start=0x800000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernelheader_addr=0x580600000\0" \
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"kernel_addr_r=0x81000000\0" \
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"kernelheader_size=0x40000\0" \
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"fdt_addr_r=0x90000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernel_size_sd=0x14000\0" \
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"console=ttyAMA0,38400n8\0" \
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"mcmemsize=0x70000000\0" \
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"sd_bootcmd=echo Trying load from SD ..;" \
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"mmcinfo; mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd && " \
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"bootm $load_addr#$board\0" \
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QSPI_MC_INIT_CMD \
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BOOTENV \
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"boot_scripts=ls2088ardb_boot.scr\0" \
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"boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"qspi_bootcmd=echo Trying load from qspi..;" \
|
|
"sf probe && sf read $load_addr " \
|
|
"$kernel_start $kernel_size ; env exists secureboot &&" \
|
|
"sf read $kernelheader_addr_r $kernelheader_start " \
|
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
|
" bootm $load_addr#$board\0" \
|
|
"nor_bootcmd=echo Trying load from nor..;" \
|
|
"cp.b $kernel_addr $load_addr " \
|
|
"$kernel_size ; env exists secureboot && " \
|
|
"cp.b $kernelheader_addr $kernelheader_addr_r " \
|
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
|
"bootm $load_addr#$board\0"
|
|
#else
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
|
"ramdisk_addr=0x800000\0" \
|
|
"ramdisk_size=0x2000000\0" \
|
|
"fdt_high=0xa0000000\0" \
|
|
"initrd_high=0xffffffffffffffff\0" \
|
|
"fdt_addr=0x64f00000\0" \
|
|
"kernel_addr=0x581000000\0" \
|
|
"kernel_start=0x1000000\0" \
|
|
"kernelheader_start=0x600000\0" \
|
|
"scriptaddr=0x80000000\0" \
|
|
"scripthdraddr=0x80080000\0" \
|
|
"fdtheader_addr_r=0x80100000\0" \
|
|
"kernelheader_addr_r=0x80200000\0" \
|
|
"kernelheader_addr=0x580600000\0" \
|
|
"kernel_addr_r=0x81000000\0" \
|
|
"kernelheader_size=0x40000\0" \
|
|
"fdt_addr_r=0x90000000\0" \
|
|
"load_addr=0xa0000000\0" \
|
|
"kernel_size=0x2800000\0" \
|
|
"kernel_addr_sd=0x8000\0" \
|
|
"kernel_size_sd=0x14000\0" \
|
|
"console=ttyAMA0,38400n8\0" \
|
|
"mcmemsize=0x70000000\0" \
|
|
"sd_bootcmd=echo Trying load from SD ..;" \
|
|
"mmcinfo; mmc read $load_addr " \
|
|
"$kernel_addr_sd $kernel_size_sd && " \
|
|
"bootm $load_addr#$board\0" \
|
|
MC_INIT_CMD \
|
|
BOOTENV \
|
|
"boot_scripts=ls2088ardb_boot.scr\0" \
|
|
"boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
|
|
"scan_dev_for_boot_part=" \
|
|
"part list ${devtype} ${devnum} devplist; " \
|
|
"env exists devplist || setenv devplist 1; " \
|
|
"for distro_bootpart in ${devplist}; do " \
|
|
"if fstype ${devtype} " \
|
|
"${devnum}:${distro_bootpart} " \
|
|
"bootfstype; then " \
|
|
"run scan_dev_for_boot; " \
|
|
"fi; " \
|
|
"done\0" \
|
|
"boot_a_script=" \
|
|
"load ${devtype} ${devnum}:${distro_bootpart} " \
|
|
"${scriptaddr} ${prefix}${script}; " \
|
|
"env exists secureboot && load ${devtype} " \
|
|
"${devnum}:${distro_bootpart} " \
|
|
"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
|
|
"env exists secureboot " \
|
|
"&& esbc_validate ${scripthdraddr};" \
|
|
"source ${scriptaddr}\0" \
|
|
"qspi_bootcmd=echo Trying load from qspi..;" \
|
|
"sf probe && sf read $load_addr " \
|
|
"$kernel_start $kernel_size ; env exists secureboot &&" \
|
|
"sf read $kernelheader_addr_r $kernelheader_start " \
|
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
|
" bootm $load_addr#$board\0" \
|
|
"nor_bootcmd=echo Trying load from nor..;" \
|
|
"cp.b $kernel_addr $load_addr " \
|
|
"$kernel_size ; env exists secureboot && " \
|
|
"cp.b $kernelheader_addr $kernelheader_addr_r " \
|
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
|
"bootm $load_addr#$board\0"
|
|
#endif
|
|
|
|
#ifdef CONFIG_TFABOOT
|
|
#define QSPI_NOR_BOOTCOMMAND \
|
|
"sf probe 0:0; " \
|
|
"sf read 0x806c0000 0x6c0000 0x40000; " \
|
|
"env exists mcinitcmd && env exists secureboot "\
|
|
"&& esbc_validate 0x806c0000; " \
|
|
"sf read 0x80d00000 0xd00000 0x100000; " \
|
|
"env exists mcinitcmd && " \
|
|
"fsl_mc lazyapply dpl 0x80d00000; " \
|
|
"run distro_bootcmd;run qspi_bootcmd; " \
|
|
"env exists secureboot && esbc_halt;"
|
|
|
|
/* Try to boot an on-SD kernel first, then do normal distro boot */
|
|
#define SD_BOOTCOMMAND \
|
|
"env exists mcinitcmd && env exists secureboot "\
|
|
"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
|
|
"&& esbc_validate $load_addr; " \
|
|
"env exists mcinitcmd && run mcinitcmd " \
|
|
"&& mmc read 0x80d00000 0x6800 0x800 " \
|
|
"&& fsl_mc lazyapply dpl 0x80d00000; " \
|
|
"run distro_bootcmd;run sd_bootcmd; " \
|
|
"env exists secureboot && esbc_halt;"
|
|
|
|
/* Try to boot an on-NOR kernel first, then do normal distro boot */
|
|
#define IFC_NOR_BOOTCOMMAND \
|
|
"env exists mcinitcmd && env exists secureboot "\
|
|
"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
|
|
"&& fsl_mc lazyapply dpl 0x580d00000;" \
|
|
"run distro_bootcmd;run nor_bootcmd; " \
|
|
"env exists secureboot && esbc_halt;"
|
|
#else
|
|
#ifdef CONFIG_QSPI_BOOT
|
|
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
|
|
#elif defined(CONFIG_SD_BOOT)
|
|
/* Try to boot an on-SD kernel first, then do normal distro boot */
|
|
#else
|
|
/* Try to boot an on-NOR kernel first, then do normal distro boot */
|
|
#endif
|
|
#endif
|
|
|
|
/* MAC/PHY configuration */
|
|
#define CORTINA_PHY_ADDR1 0x10
|
|
#define CORTINA_PHY_ADDR2 0x11
|
|
#define CORTINA_PHY_ADDR3 0x12
|
|
#define CORTINA_PHY_ADDR4 0x13
|
|
#define AQ_PHY_ADDR1 0x00
|
|
#define AQ_PHY_ADDR2 0x01
|
|
#define AQ_PHY_ADDR3 0x02
|
|
#define AQ_PHY_ADDR4 0x03
|
|
#define AQR405_IRQ_MASK 0x36
|
|
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
|
|
|
|
#include <asm/fsl_secure_boot.h>
|
|
|
|
#endif /* __LS2_RDB_H */
|