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f8f0757dcb
No need for these to be exported as they are only accessed indirectly via function pointers. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
316 lines
8.3 KiB
C
316 lines
8.3 KiB
C
/*
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* (C) Copyright 2010
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* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs
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* with an interface identical to SPI flash devices.
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* However since they behave like RAM there are no delays or
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* busy polls required. They can sustain read or write at the
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* allowed SPI bus speed, which can be 40 MHz for some devices.
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*
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* Unfortunately some RAMTRON devices do not have a means of
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* identifying them. They will leave the SO line undriven when
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* the READ-ID command is issued. It is therefore mandatory
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* that the MISO line has a proper pull-up, so that READ-ID
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* will return a row of 0xff. This 0xff pseudo-id will cause
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* probes by all vendor specific functions that are designed
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* to handle it. If the MISO line is not pulled up, READ-ID
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* could return any random noise, even mimicking another
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* device.
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*
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* We use CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
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* to define which device will be assumed after a simple status
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* register verify. This method is prone to false positive
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* detection and should therefore be the last to be tried.
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* Enter it in the last position in the table in spi_flash.c!
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*
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* The define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC both activates
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* compilation of the special handler and defines the device
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* to assume.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi_flash.h>
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#include "spi_flash_internal.h"
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/* RAMTRON commands common to all devices */
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#define CMD_RAMTRON_WREN 0x06 /* Write Enable */
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#define CMD_RAMTRON_WRDI 0x04 /* Write Disable */
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#define CMD_RAMTRON_RDSR 0x05 /* Read Status Register */
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#define CMD_RAMTRON_WRSR 0x01 /* Write Status Register */
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#define CMD_RAMTRON_READ 0x03 /* Read Data Bytes */
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#define CMD_RAMTRON_WRITE 0x02 /* Write Data Bytes */
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/* not all have those: */
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#define CMD_RAMTRON_FSTRD 0x0b /* Fast Read (for compatibility - not used here) */
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#define CMD_RAMTRON_SLEEP 0xb9 /* Enter Sleep Mode */
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#define CMD_RAMTRON_RDID 0x9f /* Read ID */
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#define CMD_RAMTRON_SNR 0xc3 /* Read Serial Number */
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/*
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* Properties of supported FRAMs
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* Note: speed is currently not used because we have no method to deliver that
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* value to the upper layers
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*/
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struct ramtron_spi_fram_params {
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u32 size; /* size in bytes */
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u8 addr_len; /* number of address bytes */
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u8 merge_cmd; /* some address bits are in the command byte */
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u8 id1; /* device ID 1 (family, density) */
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u8 id2; /* device ID 2 (sub, rev, rsvd) */
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u32 speed; /* max. SPI clock in Hz */
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const char *name; /* name for display and/or matching */
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};
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struct ramtron_spi_fram {
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struct spi_flash flash;
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const struct ramtron_spi_fram_params *params;
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};
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static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash
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*flash)
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{
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return container_of(flash, struct ramtron_spi_fram, flash);
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}
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/*
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* table describing supported FRAM chips:
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* chips without RDID command must have the values 0xff for id1 and id2
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*/
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static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = {
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{
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.size = 32*1024,
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.addr_len = 2,
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.merge_cmd = 0,
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.id1 = 0x22,
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.id2 = 0x00,
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.speed = 40000000,
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.name = "FM25V02",
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},
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{
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.size = 32*1024,
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.addr_len = 2,
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.merge_cmd = 0,
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.id1 = 0x22,
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.id2 = 0x01,
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.speed = 40000000,
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.name = "FM25VN02",
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},
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{
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.size = 64*1024,
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.addr_len = 2,
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.merge_cmd = 0,
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.id1 = 0x23,
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.id2 = 0x00,
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.speed = 40000000,
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.name = "FM25V05",
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},
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{
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.size = 64*1024,
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.addr_len = 2,
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.merge_cmd = 0,
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.id1 = 0x23,
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.id2 = 0x01,
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.speed = 40000000,
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.name = "FM25VN05",
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},
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{
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.size = 128*1024,
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.addr_len = 3,
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.merge_cmd = 0,
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.id1 = 0x24,
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.id2 = 0x00,
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.speed = 40000000,
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.name = "FM25V10",
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},
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{
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.size = 128*1024,
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.addr_len = 3,
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.merge_cmd = 0,
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.id1 = 0x24,
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.id2 = 0x01,
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.speed = 40000000,
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.name = "FM25VN10",
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},
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#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
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{
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.size = 256*1024,
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.addr_len = 3,
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.merge_cmd = 0,
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.id1 = 0xff,
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.id2 = 0xff,
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.speed = 40000000,
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.name = "FM25H20",
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},
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#endif
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};
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static int ramtron_common(struct spi_flash *flash,
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u32 offset, size_t len, void *buf, u8 command)
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{
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struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash);
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u8 cmd[4];
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int cmd_len;
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int ret;
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if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) {
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cmd[0] = command;
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cmd[1] = offset >> 16;
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cmd[2] = offset >> 8;
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cmd[3] = offset;
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cmd_len = 4;
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} else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) {
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cmd[0] = command;
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cmd[1] = offset >> 8;
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cmd[2] = offset;
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cmd_len = 3;
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} else {
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printf("SF: unsupported addr_len or merge_cmd\n");
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return -1;
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}
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/* claim the bus */
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ret = spi_claim_bus(flash->spi);
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if (ret) {
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debug("SF: Unable to claim SPI bus\n");
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return ret;
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}
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if (command == CMD_RAMTRON_WRITE) {
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/* send WREN */
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ret = spi_flash_cmd(flash->spi, CMD_RAMTRON_WREN, NULL, 0);
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if (ret < 0) {
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debug("SF: Enabling Write failed\n");
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goto releasebus;
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}
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}
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/* do the transaction */
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if (command == CMD_RAMTRON_WRITE)
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ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len);
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else
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ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len);
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if (ret < 0)
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debug("SF: Transaction failed\n");
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releasebus:
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/* release the bus */
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spi_release_bus(flash->spi);
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return ret;
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}
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static int ramtron_read(struct spi_flash *flash,
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u32 offset, size_t len, void *buf)
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{
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return ramtron_common(flash, offset, len, buf,
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CMD_RAMTRON_READ);
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}
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static int ramtron_write(struct spi_flash *flash,
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u32 offset, size_t len, const void *buf)
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{
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return ramtron_common(flash, offset, len, (void *)buf,
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CMD_RAMTRON_WRITE);
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}
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static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len)
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{
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debug("SF: Erase of RAMTRON FRAMs is pointless\n");
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return -1;
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}
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/*
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* nore: we are called here with idcode pointing to the first non-0x7f byte
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* already!
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*/
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struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
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{
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const struct ramtron_spi_fram_params *params;
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struct ramtron_spi_fram *sn;
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unsigned int i;
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#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
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int ret;
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u8 sr;
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#endif
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/* NOTE: the bus has been claimed before this function is called! */
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switch (idcode[0]) {
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case 0xc2:
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/* JEDEC conformant RAMTRON id */
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for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
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params = &ramtron_spi_fram_table[i];
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if (idcode[1] == params->id1 && idcode[2] == params->id2)
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goto found;
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}
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break;
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#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
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case 0xff:
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/*
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* probably open MISO line, pulled up.
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* We COULD have a non JEDEC conformant FRAM here,
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* read the status register to verify
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*/
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ret = spi_flash_cmd(spi, CMD_RAMTRON_RDSR, &sr, 1);
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if (ret)
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return NULL;
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/* Bits 5,4,0 are fixed 0 for all devices */
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if ((sr & 0x31) != 0x00)
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return NULL;
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/* now find the device */
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for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
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params = &ramtron_spi_fram_table[i];
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if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
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goto found;
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}
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debug("SF: Unsupported non-JEDEC RAMTRON device "
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CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "\n");
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break;
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#endif
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default:
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break;
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}
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/* arriving here means no method has found a device we can handle */
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debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n",
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idcode[0], idcode[1], idcode[2]);
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return NULL;
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found:
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sn = malloc(sizeof(*sn));
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if (!sn) {
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debug("SF: Failed to allocate memory\n");
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return NULL;
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}
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sn->params = params;
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sn->flash.spi = spi;
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sn->flash.name = params->name;
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sn->flash.write = ramtron_write;
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sn->flash.read = ramtron_read;
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sn->flash.erase = ramtron_erase;
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sn->flash.size = params->size;
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return &sn->flash;
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}
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