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u-boot/arch/x86/dts/microcode
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Bin Meng e61a2687b3 x86: braswell: Add microcode for B0/C0/D0 stepping SoC 
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-16 14:57:44 +08:00
..
m01406c440a.dtsi x86: braswell: Add microcode for B0/C0/D0 stepping SoC 2017-09-16 14:57:44 +08:00
m01406c2220.dtsi x86: braswell: Add microcode for B0/C0/D0 stepping SoC 2017-09-16 14:57:44 +08:00
m01406c3363.dtsi x86: braswell: Add microcode for B0/C0/D0 stepping SoC 2017-09-16 14:57:44 +08:00
m12206a7_00000029.dtsi
m12306a2_00000008.dtsi
m12306a4_00000007.dtsi
m12306a5_00000007.dtsi
m12306a8_00000010.dtsi
m12306a9_0000001b.dtsi
m7240651_0000001c.dtsi
m0130673325.dtsi
m0130679907.dtsi
m0220661105_cv.dtsi
m0230671117.dtsi
mc0306d4_00000018.dtsi