mirror of
https://github.com/AsahiLinux/u-boot
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0e35bde7b1
* For cold silicon the DDR timings need to be relaxed in order for the device to boot with DDR at 266MHz * Fix proposed by James Doublesin Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
264 lines
6.8 KiB
C
264 lines
6.8 KiB
C
/*
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* ddr_defs.h
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*
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* ddr specific header
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DDR_DEFS_H
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#define _DDR_DEFS_H
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#include <asm/arch/hardware.h>
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/* AM335X EMIF Register values */
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#define EMIF_SDMGT 0x80000000
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#define EMIF_SDRAM 0x00004650
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#define EMIF_PHYCFG 0x2
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#define DDR_PHY_RESET (0x1 << 10)
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#define DDR_FUNCTIONAL_MODE_EN 0x1
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#define DDR_PHY_READY (0x1 << 2)
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#define VTP_CTRL_READY (0x1 << 5)
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#define VTP_CTRL_ENABLE (0x1 << 6)
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#define VTP_CTRL_LOCK_EN (0x1 << 4)
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#define VTP_CTRL_START_EN (0x1)
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#define DDR2_RATIO 0x80
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#define CMD_FORCE 0x00
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#define CMD_DELAY 0x00
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#define EMIF_READ_LATENCY 0x05
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#define EMIF_TIM1 0x0666B3D6
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#define EMIF_TIM2 0x143731DA
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#define EMIF_TIM3 0x00000347
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#define EMIF_SDCFG 0x43805332
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#define EMIF_SDREF 0x0000081a
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#define DDR2_DLL_LOCK_DIFF 0x0
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#define DDR2_RD_DQS 0x12
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#define DDR2_PHY_FIFO_WE 0x80
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#define DDR2_INVERT_CLKOUT 0x00
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#define DDR2_WR_DQS 0x00
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#define DDR2_PHY_WRLVL 0x00
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#define DDR2_PHY_GATELVL 0x00
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#define DDR2_PHY_WR_DATA 0x40
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#define PHY_RANK0_DELAY 0x01
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#define PHY_DLL_LOCK_DIFF 0x0
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#define DDR_IOCTRL_VALUE 0x18B
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/**
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* This structure represents the EMIF registers on AM33XX devices.
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*/
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struct emif_regs {
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unsigned int sdrrev; /* offset 0x00 */
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unsigned int sdrstat; /* offset 0x04 */
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unsigned int sdrcr; /* offset 0x08 */
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unsigned int sdrcr2; /* offset 0x0C */
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unsigned int sdrrcr; /* offset 0x10 */
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unsigned int sdrrcsr; /* offset 0x14 */
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unsigned int sdrtim1; /* offset 0x18 */
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unsigned int sdrtim1sr; /* offset 0x1C */
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unsigned int sdrtim2; /* offset 0x20 */
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unsigned int sdrtim2sr; /* offset 0x24 */
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unsigned int sdrtim3; /* offset 0x28 */
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unsigned int sdrtim3sr; /* offset 0x2C */
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unsigned int res1[2];
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unsigned int sdrmcr; /* offset 0x38 */
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unsigned int sdrmcsr; /* offset 0x3C */
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unsigned int res2[8];
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unsigned int sdritr; /* offset 0x60 */
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unsigned int res3[32];
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unsigned int ddrphycr; /* offset 0xE4 */
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unsigned int ddrphycsr; /* offset 0xE8 */
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unsigned int ddrphycr2; /* offset 0xEC */
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};
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/**
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* Encapsulates DDR PHY control and corresponding shadow registers.
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*/
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struct ddr_phy_control {
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unsigned long reg;
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unsigned long reg_sh;
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unsigned long reg2;
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};
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/**
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* Encapsulates SDRAM timing and corresponding shadow registers.
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*/
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struct sdram_timing {
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unsigned long time1;
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unsigned long time1_sh;
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unsigned long time2;
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unsigned long time2_sh;
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unsigned long time3;
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unsigned long time3_sh;
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};
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/**
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* Encapsulates SDRAM configuration.
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* (Includes refresh control registers) */
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struct sdram_config {
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unsigned long sdrcr;
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unsigned long sdrcr2;
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unsigned long refresh;
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unsigned long refresh_sh;
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};
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/**
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* Configure SDRAM
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*/
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int config_sdram(struct sdram_config *cfg);
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/**
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* Set SDRAM timings
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*/
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int set_sdram_timings(struct sdram_timing *val);
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/**
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* Configure DDR PHY
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*/
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int config_ddr_phy(struct ddr_phy_control *cfg);
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/**
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* This structure represents the DDR registers on AM33XX devices.
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*/
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struct ddr_regs {
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unsigned int resv0[7];
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unsigned int cm0csratio; /* offset 0x01C */
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unsigned int cm0csforce; /* offset 0x020 */
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unsigned int cm0csdelay; /* offset 0x024 */
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unsigned int cm0dldiff; /* offset 0x028 */
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unsigned int cm0iclkout; /* offset 0x02C */
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unsigned int resv1[8];
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unsigned int cm1csratio; /* offset 0x050 */
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unsigned int cm1csforce; /* offset 0x054 */
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unsigned int cm1csdelay; /* offset 0x058 */
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unsigned int cm1dldiff; /* offset 0x05C */
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unsigned int cm1iclkout; /* offset 0x060 */
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unsigned int resv2[8];
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unsigned int cm2csratio; /* offset 0x084 */
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unsigned int cm2csforce; /* offset 0x088 */
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unsigned int cm2csdelay; /* offset 0x08C */
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unsigned int cm2dldiff; /* offset 0x090 */
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unsigned int cm2iclkout; /* offset 0x094 */
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unsigned int resv3[12];
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unsigned int dt0rdsratio0; /* offset 0x0C8 */
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unsigned int dt0rdsratio1; /* offset 0x0CC */
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unsigned int resv4[3];
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unsigned int dt0wdsratio0; /* offset 0x0DC */
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unsigned int dt0wdsratio1; /* offset 0x0E0 */
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unsigned int resv5[3];
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unsigned int dt0wiratio0; /* offset 0x0F0 */
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unsigned int dt0wiratio1; /* offset 0x0F4 */
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unsigned int dt0giratio0; /* offset 0x0FC */
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unsigned int dt0giratio1; /* offset 0x100 */
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unsigned int resv6[1];
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unsigned int dt0fwsratio0; /* offset 0x108 */
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unsigned int dt0fwsratio1; /* offset 0x10C */
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unsigned int resv7[4];
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unsigned int dt0wrsratio0; /* offset 0x120 */
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unsigned int dt0wrsratio1; /* offset 0x124 */
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unsigned int resv8[3];
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unsigned int dt0rdelays0; /* offset 0x134 */
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unsigned int dt0dldiff0; /* offset 0x138 */
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unsigned int resv9[39];
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unsigned int dt1rdelays0; /* offset 0x1D8 */
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};
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/**
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* Encapsulates DDR CMD control registers.
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*/
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struct cmd_control {
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unsigned long cmd0csratio;
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unsigned long cmd0csforce;
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unsigned long cmd0csdelay;
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unsigned long cmd0dldiff;
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unsigned long cmd0iclkout;
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unsigned long cmd1csratio;
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unsigned long cmd1csforce;
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unsigned long cmd1csdelay;
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unsigned long cmd1dldiff;
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unsigned long cmd1iclkout;
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unsigned long cmd2csratio;
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unsigned long cmd2csforce;
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unsigned long cmd2csdelay;
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unsigned long cmd2dldiff;
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unsigned long cmd2iclkout;
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};
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/**
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* Encapsulates DDR DATA registers.
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*/
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struct ddr_data {
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unsigned long datardsratio0;
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unsigned long datardsratio1;
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unsigned long datawdsratio0;
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unsigned long datawdsratio1;
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unsigned long datawiratio0;
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unsigned long datawiratio1;
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unsigned long datagiratio0;
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unsigned long datagiratio1;
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unsigned long datafwsratio0;
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unsigned long datafwsratio1;
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unsigned long datawrsratio0;
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unsigned long datawrsratio1;
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unsigned long datadldiff0;
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};
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/**
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* Configure DDR CMD control registers
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*/
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int config_cmd_ctrl(struct cmd_control *cmd);
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/**
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* Configure DDR DATA registers
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*/
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int config_ddr_data(int data_macrono, struct ddr_data *data);
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/**
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* This structure represents the DDR io control on AM33XX devices.
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*/
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struct ddr_cmdtctrl {
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unsigned int resv1[1];
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unsigned int cm0ioctl;
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unsigned int cm1ioctl;
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unsigned int cm2ioctl;
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unsigned int resv2[12];
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unsigned int dt0ioctl;
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unsigned int dt1ioctl;
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};
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/**
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* Encapsulates DDR CMD & DATA io control registers.
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*/
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struct ddr_ioctrl {
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unsigned long cmd1ctl;
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unsigned long cmd2ctl;
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unsigned long cmd3ctl;
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unsigned long data1ctl;
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unsigned long data2ctl;
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};
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/**
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* Configure DDR io control registers
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*/
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int config_io_ctrl(struct ddr_ioctrl *ioctrl);
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struct ddr_ctrl {
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unsigned int ddrioctrl;
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unsigned int resv1[325];
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unsigned int ddrckectrl;
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};
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void config_ddr(void);
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#endif /* _DDR_DEFS_H */
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