u-boot/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
Marek Vasut 98fe251a24 ARM: dts: stm32: Add custom PHY reset bindings on AV96
The ethernet PHY must be reset on AV96, however DWMAC currently does
not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC
PHY reset property is going away on next DT sync. Add PHY specific
reset bindings to trigger the PHY reset and fix sporadic ethernet
malfunctions, until the next DT sync.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-13 14:34:11 +01:00

97 lines
1.2 KiB
Text

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcor-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
usb0 = &usbotg_hs;
};
config {
u-boot,boot-led = "led1";
u-boot,error-led = "led4";
dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>;
};
};
&ethernet0 {
mdio0 {
ethernet-phy@7 {
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <1000>;
};
};
};
&sdmmc1 {
u-boot,dm-spl;
};
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc1_dir_pins_b {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2 {
u-boot,dm-spl;
};
&sdmmc2_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2_d47_pins_c {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_b {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
/delete-property/ bias-disable;
bias-pull-up;
};
};
&usbotg_hs {
u-boot,force-b-session-valid;
hnp-srp-disable;
};