mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 01:17:39 +00:00
ec0f9530b1
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
502 lines
14 KiB
C
502 lines
14 KiB
C
/*
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* Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/hab.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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/* -------- start of HAB API updates ------------*/
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#define hab_rvt_report_event_p \
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( \
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((is_cpu_type(MXC_CPU_MX6Q) || \
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is_cpu_type(MXC_CPU_MX6D)) && \
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(soc_rev() >= CHIP_REV_1_5)) ? \
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((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
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(is_cpu_type(MXC_CPU_MX6DL) && \
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(soc_rev() >= CHIP_REV_1_2)) ? \
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((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
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((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
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)
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#define hab_rvt_report_status_p \
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( \
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((is_cpu_type(MXC_CPU_MX6Q) || \
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is_cpu_type(MXC_CPU_MX6D)) && \
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(soc_rev() >= CHIP_REV_1_5)) ? \
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((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
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(is_cpu_type(MXC_CPU_MX6DL) && \
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(soc_rev() >= CHIP_REV_1_2)) ? \
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((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
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((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
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)
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#define hab_rvt_authenticate_image_p \
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( \
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((is_cpu_type(MXC_CPU_MX6Q) || \
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is_cpu_type(MXC_CPU_MX6D)) && \
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(soc_rev() >= CHIP_REV_1_5)) ? \
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((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
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(is_cpu_type(MXC_CPU_MX6DL) && \
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(soc_rev() >= CHIP_REV_1_2)) ? \
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((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
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((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
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)
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#define hab_rvt_entry_p \
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( \
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((is_cpu_type(MXC_CPU_MX6Q) || \
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is_cpu_type(MXC_CPU_MX6D)) && \
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(soc_rev() >= CHIP_REV_1_5)) ? \
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((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
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(is_cpu_type(MXC_CPU_MX6DL) && \
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(soc_rev() >= CHIP_REV_1_2)) ? \
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((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
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((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
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)
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#define hab_rvt_exit_p \
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( \
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((is_cpu_type(MXC_CPU_MX6Q) || \
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is_cpu_type(MXC_CPU_MX6D)) && \
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(soc_rev() >= CHIP_REV_1_5)) ? \
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((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
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(is_cpu_type(MXC_CPU_MX6DL) && \
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(soc_rev() >= CHIP_REV_1_2)) ? \
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((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
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((hab_rvt_exit_t *)HAB_RVT_EXIT) \
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)
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#define IVT_SIZE 0x20
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#define ALIGN_SIZE 0x1000
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#define CSF_PAD_SIZE 0x2000
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#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
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#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
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#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
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/*
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* +------------+ 0x0 (DDR_UIMAGE_START) -
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* | Header | |
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* +------------+ 0x40 |
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* | | |
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* | | |
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* | | |
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* | | |
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* | Image Data | |
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* . | |
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* . | > Stuff to be authenticated ----+
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* . | | |
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* | | | |
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* | | | |
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* +------------+ | |
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* | | | |
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* | Fill Data | | |
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* | | | |
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* +------------+ Align to ALIGN_SIZE | |
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* | IVT | | |
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* +------------+ + IVT_SIZE - |
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* | | |
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* | CSF DATA | <---------------------------------------------------------+
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* | |
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* +------------+
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* | |
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* | Fill Data |
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* | |
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* +------------+ + CSF_PAD_SIZE
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*/
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#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
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struct record {
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uint8_t tag; /* Tag */
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uint8_t len[2]; /* Length */
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uint8_t par; /* Version */
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uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
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bool any_rec_flag;
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};
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char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
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"RSN = HAB_ENG_FAIL (0x30)\n",
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"RSN = HAB_INV_ADDRESS (0x22)\n",
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"RSN = HAB_INV_ASSERTION (0x0C)\n",
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"RSN = HAB_INV_CALL (0x28)\n",
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"RSN = HAB_INV_CERTIFICATE (0x21)\n",
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"RSN = HAB_INV_COMMAND (0x06)\n",
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"RSN = HAB_INV_CSF (0x11)\n",
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"RSN = HAB_INV_DCD (0x27)\n",
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"RSN = HAB_INV_INDEX (0x0F)\n",
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"RSN = HAB_INV_IVT (0x05)\n",
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"RSN = HAB_INV_KEY (0x1D)\n",
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"RSN = HAB_INV_RETURN (0x1E)\n",
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"RSN = HAB_INV_SIGNATURE (0x18)\n",
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"RSN = HAB_INV_SIZE (0x17)\n",
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"RSN = HAB_MEM_FAIL (0x2E)\n",
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"RSN = HAB_OVR_COUNT (0x2B)\n",
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"RSN = HAB_OVR_STORAGE (0x2D)\n",
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"RSN = HAB_UNS_ALGORITHM (0x12)\n",
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"RSN = HAB_UNS_COMMAND (0x03)\n",
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"RSN = HAB_UNS_ENGINE (0x0A)\n",
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"RSN = HAB_UNS_ITEM (0x24)\n",
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"RSN = HAB_UNS_KEY (0x1B)\n",
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"RSN = HAB_UNS_PROTOCOL (0x14)\n",
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"RSN = HAB_UNS_STATE (0x09)\n",
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"RSN = INVALID\n",
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NULL};
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char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
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"STS = HAB_FAILURE (0x33)\n",
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"STS = HAB_WARNING (0x69)\n",
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"STS = INVALID\n",
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NULL};
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char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
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"ENG = HAB_ENG_SCC (0x03)\n",
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"ENG = HAB_ENG_RTIC (0x05)\n",
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"ENG = HAB_ENG_SAHARA (0x06)\n",
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"ENG = HAB_ENG_CSU (0x0A)\n",
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"ENG = HAB_ENG_SRTC (0x0C)\n",
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"ENG = HAB_ENG_DCP (0x1B)\n",
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"ENG = HAB_ENG_CAAM (0x1D)\n",
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"ENG = HAB_ENG_SNVS (0x1E)\n",
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"ENG = HAB_ENG_OCOTP (0x21)\n",
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"ENG = HAB_ENG_DTCP (0x22)\n",
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"ENG = HAB_ENG_ROM (0x36)\n",
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"ENG = HAB_ENG_HDCP (0x24)\n",
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"ENG = HAB_ENG_RTL (0x77)\n",
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"ENG = HAB_ENG_SW (0xFF)\n",
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"ENG = INVALID\n",
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NULL};
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char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
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"CTX = HAB_CTX_FAB (0xFF)\n",
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"CTX = HAB_CTX_ENTRY (0xE1)\n",
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"CTX = HAB_CTX_TARGET (0x33)\n",
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"CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
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"CTX = HAB_CTX_DCD (0xDD)\n",
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"CTX = HAB_CTX_CSF (0xCF)\n",
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"CTX = HAB_CTX_COMMAND (0xC0)\n",
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"CTX = HAB_CTX_AUT_DAT (0xDB)\n",
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"CTX = HAB_CTX_ASSERT (0xA0)\n",
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"CTX = HAB_CTX_EXIT (0xEE)\n",
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"CTX = INVALID\n",
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NULL};
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uint8_t hab_statuses[5] = {
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HAB_STS_ANY,
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HAB_FAILURE,
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HAB_WARNING,
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HAB_SUCCESS,
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-1
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};
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uint8_t hab_reasons[26] = {
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HAB_RSN_ANY,
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HAB_ENG_FAIL,
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HAB_INV_ADDRESS,
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HAB_INV_ASSERTION,
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HAB_INV_CALL,
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HAB_INV_CERTIFICATE,
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HAB_INV_COMMAND,
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HAB_INV_CSF,
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HAB_INV_DCD,
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HAB_INV_INDEX,
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HAB_INV_IVT,
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HAB_INV_KEY,
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HAB_INV_RETURN,
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HAB_INV_SIGNATURE,
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HAB_INV_SIZE,
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HAB_MEM_FAIL,
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HAB_OVR_COUNT,
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HAB_OVR_STORAGE,
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HAB_UNS_ALGORITHM,
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HAB_UNS_COMMAND,
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HAB_UNS_ENGINE,
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HAB_UNS_ITEM,
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HAB_UNS_KEY,
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HAB_UNS_PROTOCOL,
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HAB_UNS_STATE,
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-1
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};
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uint8_t hab_contexts[12] = {
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HAB_CTX_ANY,
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HAB_CTX_FAB,
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HAB_CTX_ENTRY,
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HAB_CTX_TARGET,
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HAB_CTX_AUTHENTICATE,
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HAB_CTX_DCD,
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HAB_CTX_CSF,
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HAB_CTX_COMMAND,
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HAB_CTX_AUT_DAT,
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HAB_CTX_ASSERT,
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HAB_CTX_EXIT,
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-1
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};
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uint8_t hab_engines[16] = {
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HAB_ENG_ANY,
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HAB_ENG_SCC,
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HAB_ENG_RTIC,
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HAB_ENG_SAHARA,
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HAB_ENG_CSU,
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HAB_ENG_SRTC,
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HAB_ENG_DCP,
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HAB_ENG_CAAM,
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HAB_ENG_SNVS,
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HAB_ENG_OCOTP,
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HAB_ENG_DTCP,
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HAB_ENG_ROM,
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HAB_ENG_HDCP,
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HAB_ENG_RTL,
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HAB_ENG_SW,
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-1
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};
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bool is_hab_enabled(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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uint32_t reg = readl(&fuse->cfg5);
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return (reg & 0x2) == 0x2;
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}
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static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
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{
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uint8_t idx = 0;
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uint8_t element = list[idx];
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while (element != -1) {
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if (element == tgt)
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return idx;
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element = list[++idx];
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}
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return -1;
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}
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void process_event_record(uint8_t *event_data, size_t bytes)
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{
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struct record *rec = (struct record *)event_data;
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printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
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printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
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printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
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printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
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}
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void display_event(uint8_t *event_data, size_t bytes)
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{
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uint32_t i;
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if (!(event_data && bytes > 0))
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return;
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for (i = 0; i < bytes; i++) {
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if (i == 0)
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printf("\t0x%02x", event_data[i]);
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else if ((i % 8) == 0)
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printf("\n\t0x%02x", event_data[i]);
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else
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printf(" 0x%02x", event_data[i]);
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}
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process_event_record(event_data, bytes);
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}
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int get_hab_status(void)
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{
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uint32_t index = 0; /* Loop index */
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uint8_t event_data[128]; /* Event data buffer */
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size_t bytes = sizeof(event_data); /* Event size in bytes */
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enum hab_config config = 0;
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enum hab_state state = 0;
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hab_rvt_report_event_t *hab_rvt_report_event;
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hab_rvt_report_status_t *hab_rvt_report_status;
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hab_rvt_report_event = hab_rvt_report_event_p;
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hab_rvt_report_status = hab_rvt_report_status_p;
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if (is_hab_enabled())
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puts("\nSecure boot enabled\n");
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else
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puts("\nSecure boot disabled\n");
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/* Check HAB status */
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if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
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printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
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config, state);
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/* Display HAB Error events */
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while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
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&bytes) == HAB_SUCCESS) {
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puts("\n");
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printf("--------- HAB Event %d -----------------\n",
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index + 1);
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puts("event data:\n");
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display_event(event_data, bytes);
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puts("\n");
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bytes = sizeof(event_data);
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index++;
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}
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}
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/* Display message if no HAB events are found */
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else {
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printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
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config, state);
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puts("No HAB Events Found!\n\n");
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}
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return 0;
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}
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uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
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{
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uint32_t load_addr = 0;
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size_t bytes;
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ptrdiff_t ivt_offset = 0;
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int result = 0;
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ulong start;
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hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
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hab_rvt_entry_t *hab_rvt_entry;
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hab_rvt_exit_t *hab_rvt_exit;
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hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
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hab_rvt_entry = hab_rvt_entry_p;
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hab_rvt_exit = hab_rvt_exit_p;
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if (is_hab_enabled()) {
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printf("\nAuthenticate image from DDR location 0x%x...\n",
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ddr_start);
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hab_caam_clock_enable(1);
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if (hab_rvt_entry() == HAB_SUCCESS) {
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/* If not already aligned, Align to ALIGN_SIZE */
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ivt_offset = (image_size + ALIGN_SIZE - 1) &
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~(ALIGN_SIZE - 1);
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start = ddr_start;
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bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
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#ifdef DEBUG
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printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
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ivt_offset, ddr_start + ivt_offset);
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puts("Dumping IVT\n");
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print_buffer(ddr_start + ivt_offset,
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(void *)(ddr_start + ivt_offset),
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4, 0x8, 0);
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puts("Dumping CSF Header\n");
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print_buffer(ddr_start + ivt_offset+IVT_SIZE,
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(void *)(ddr_start + ivt_offset+IVT_SIZE),
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4, 0x10, 0);
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get_hab_status();
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puts("\nCalling authenticate_image in ROM\n");
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printf("\tivt_offset = 0x%x\n", ivt_offset);
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printf("\tstart = 0x%08lx\n", start);
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printf("\tbytes = 0x%x\n", bytes);
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#endif
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/*
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* If the MMU is enabled, we have to notify the ROM
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* code, or it won't flush the caches when needed.
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* This is done, by setting the "pu_irom_mmu_enabled"
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* word to 1. You can find its address by looking in
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* the ROM map. This is critical for
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* authenticate_image(). If MMU is enabled, without
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* setting this bit, authentication will fail and may
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* crash.
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*/
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/* Check MMU enabled */
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if (get_cr() & CR_M) {
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if (is_cpu_type(MXC_CPU_MX6Q) ||
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is_cpu_type(MXC_CPU_MX6D)) {
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/*
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* This won't work on Rev 1.0.0 of
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* i.MX6Q/D, since their ROM doesn't
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* do cache flushes. don't think any
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* exist, so we ignore them.
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*/
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if (!is_mx6dqp())
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writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
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} else if (is_cpu_type(MXC_CPU_MX6DL) ||
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is_cpu_type(MXC_CPU_MX6SOLO)) {
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writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
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} else if (is_cpu_type(MXC_CPU_MX6SL)) {
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writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
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}
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}
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load_addr = (uint32_t)hab_rvt_authenticate_image(
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HAB_CID_UBOOT,
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ivt_offset, (void **)&start,
|
|
(size_t *)&bytes, NULL);
|
|
if (hab_rvt_exit() != HAB_SUCCESS) {
|
|
puts("hab exit function fail\n");
|
|
load_addr = 0;
|
|
}
|
|
} else {
|
|
puts("hab entry function fail\n");
|
|
}
|
|
|
|
hab_caam_clock_enable(0);
|
|
|
|
get_hab_status();
|
|
} else {
|
|
puts("hab fuse not enabled\n");
|
|
}
|
|
|
|
if ((!is_hab_enabled()) || (load_addr != 0))
|
|
result = 1;
|
|
|
|
return result;
|
|
}
|
|
|
|
int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
if ((argc != 1)) {
|
|
cmd_usage(cmdtp);
|
|
return 1;
|
|
}
|
|
|
|
get_hab_status();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
|
|
char * const argv[])
|
|
{
|
|
ulong addr, ivt_offset;
|
|
int rcode = 0;
|
|
|
|
if (argc < 3)
|
|
return CMD_RET_USAGE;
|
|
|
|
addr = simple_strtoul(argv[1], NULL, 16);
|
|
ivt_offset = simple_strtoul(argv[2], NULL, 16);
|
|
|
|
rcode = authenticate_image(addr, ivt_offset);
|
|
|
|
return rcode;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
|
|
"display HAB status",
|
|
""
|
|
);
|
|
|
|
U_BOOT_CMD(
|
|
hab_auth_img, 3, 0, do_authenticate_image,
|
|
"authenticate image via HAB",
|
|
"addr ivt_offset\n"
|
|
"addr - image hex address\n"
|
|
"ivt_offset - hex offset of IVT in the image"
|
|
);
|