mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
f82107f637
This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to enalbe_mpc8569mds_qe_uec which is more accurate. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
66 lines
2.2 KiB
C
66 lines
2.2 KiB
C
/*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include "bcsr.h"
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void enable_8569mds_flash_write()
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{
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
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}
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void disable_8569mds_flash_write()
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{
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
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}
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void enable_8569mds_qe_uec()
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{
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#if defined(CONFIG_SYS_UCC_RGMII_MODE)
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
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BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
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BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
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BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
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BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
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#elif defined(CONFIG_SYS_UCC_RMII_MODE)
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/* Set UCC1-4 working at RMII mode */
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
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BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
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BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
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BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
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BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
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setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
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#endif
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}
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void disable_8569mds_brd_eeprom_write_protect()
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{
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clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
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}
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