mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 14:53:06 +00:00
601483ffd5
This converts the following to Kconfig: CONFIG_KEY_REVOCATION CONFIG_SYS_FSL_SFP_BE CONFIG_SYS_FSL_SFP_LE CONFIG_SYS_FSL_SFP_VER_3_0 CONFIG_SYS_FSL_SFP_VER_3_2 CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SRK_LE This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for when CHAIN_OF_TRUST is enabled. Signed-off-by: Tom Rini <trini@konsulko.com>
343 lines
10 KiB
C
343 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016-2018, 2020 NXP
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* Copyright 2015, Freescale Semiconductor
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*/
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#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
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#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
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#include <linux/kconfig.h>
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#include <fsl_ddrc_version.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
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/*
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* Reserve secure memory
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* To be aligned with MMU block size
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*/
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#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
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#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
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#ifdef CONFIG_ARCH_LS2080A
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#define SRDS_MAX_LANES 8
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#ifndef L1_CACHE_BYTES
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
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#endif
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
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/* DDR */
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_IFC_LE
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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/* Cache Coherent Interconnect */
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#define CCI_MN_BASE 0x04000000
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#define CCI_MN_RNF_NODEID_LIST 0x180
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#define CCI_MN_DVM_DOMAIN_CTL 0x200
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#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
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#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
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#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
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#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
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#define CCN_HN_F_SAM_NODEID_MASK 0x7f
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#define CCN_HN_F_SAM_NODEID_DDR0 0x4
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#define CCN_HN_F_SAM_NODEID_DDR1 0xe
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#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
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#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
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#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
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#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
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#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
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#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
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#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
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#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
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#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
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#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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#define TZPCR0SIZE_BASE (TZPC_BASE)
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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#define DCSR_CGACRE5 0x700070914ULL
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#define EPU_EPCMPR5 0x700060914ULL
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#define EPU_EPCCR5 0x700060814ULL
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#define EPU_EPSMCR5 0x700060228ULL
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#define EPU_EPECR5 0x700060314ULL
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#define EPU_EPCTR5 0x700060a14ULL
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#define EPU_EPGCR 0x700060000ULL
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#define CONFIG_SYS_FSL_ERRATUM_A008751
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#elif defined(CONFIG_ARCH_LS1088A)
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define SRDS_MAX_LANES 4
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#define SRDS_BITS_PER_LANE 4
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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#define TZPCR0SIZE_BASE (TZPC_BASE)
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DDR */
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_IFC_LE
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
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/* LX2160A/LX2162A Soc Support */
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#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
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#define TZPC_BASE 0x02200000
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define SRDS_MAX_LANES 8
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#ifndef L1_CACHE_BYTES
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
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#endif
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
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/* DDR */
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06200000
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/* SMMU Definitions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#elif defined(CONFIG_ARCH_LS1028A)
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
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#define CONFIG_FSL_TZASC_400
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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#define TZPCR0SIZE_BASE (TZPC_BASE)
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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#define SRDS_MAX_LANES 4
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#define SRDS_BITS_PER_LANE 4
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06040000
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/* SMMU Definitions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DDR */
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* SEC */
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#elif defined(CONFIG_FSL_LSCH2)
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
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#define DCSR_DCFG_SBEESR2 0x20140534
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#define DCSR_DCFG_MBEESR2 0x20140544
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#define CONFIG_SYS_FSL_CCSR_SCFG_BE
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#define CONFIG_SYS_FSL_ESDHC_BE
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#define CONFIG_SYS_FSL_WDOG_BE
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#define CONFIG_SYS_FSL_DSPI_BE
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#define CONFIG_SYS_FSL_CCSR_GUR_BE
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#define CONFIG_SYS_FSL_PEX_LUT_BE
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/* SoC related */
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#ifdef CONFIG_ARCH_LS1043A
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#define CONFIG_SYS_FMAN_V3
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#define CONFIG_SYS_FSL_QMAN_V3
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 7
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_IFC_BE
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/* SMMU Defintions */
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#define SMMU_BASE 0x09000000
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x01401000
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#define GICC_BASE 0x01402000
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#define GICH_BASE 0x01404000
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#define GICV_BASE 0x01406000
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#define GICD_SIZE 0x1000
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#define GICC_SIZE 0x2000
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#define GICH_SIZE 0x2000
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#define GICV_SIZE 0x2000
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#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
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#define GICD_BASE_64K 0x01410000
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#define GICC_BASE_64K 0x01420000
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#define GICH_BASE_64K 0x01440000
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#define GICV_BASE_64K 0x01460000
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#define GICD_SIZE_64K 0x10000
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#define GICC_SIZE_64K 0x20000
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#define GICH_SIZE_64K 0x20000
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#define GICV_SIZE_64K 0x20000
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#endif
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#define DCFG_CCSR_SVR 0x1ee00a4
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#define REV1_0 0x10
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#define REV1_1 0x11
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#define GIC_ADDR_BIT 31
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#define SCFG_GIC400_ALIGN 0x1570188
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#elif defined(CONFIG_ARCH_LS1012A)
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#define GICD_BASE 0x01401000
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#define GICC_BASE 0x01402000
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#elif defined(CONFIG_ARCH_LS1046A)
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#define CONFIG_SYS_FMAN_V3
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#define CONFIG_SYS_FSL_QMAN_V3
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 8
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#define CONFIG_SYS_NUM_FM1_10GEC 2
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_IFC_BE
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/* SMMU Defintions */
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#define SMMU_BASE 0x09000000
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x01410000
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#define GICC_BASE 0x01420000
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#else
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#error SoC not defined
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#endif
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#endif
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#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
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