mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-23 16:11:54 +00:00
f76750d111
This converts the following to Kconfig: CONFIG_CONS_INDEX CONFIG_DEBUG_UART_CLOCK CONFIG_FSL_TZPC_BP147 CONFIG_GENERIC_ATMEL_MCI CONFIG_IDENT_STRING CONFIG_LIBATA CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_LPC32XX_GPIO CONFIG_MP CONFIG_MPC8XXX_GPIO CONFIG_MTD_PARTITIONS CONFIG_MVGBE CONFIG_MXC_GPIO CONFIG_NR_DRAM_BANKS CONFIG_OF_BOARD_SETUP CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_OF_SYSTEM_SETUP CONFIG_PREBOOT CONFIG_ROCKCHIP_SERIAL CONFIG_RTC_ENABLE_32KHZ_OUTPUT CONFIG_RTC_MV CONFIG_SCSI_AHCI CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_SPEED CONFIG_SOFT_SPI CONFIG_SPI_FLASH_EON CONFIG_SPI_FLASH_MACRONIX CONFIG_SPI_FLASH_MTD CONFIG_SPI_FLASH_SPANSION CONFIG_SPI_FLASH_SST CONFIG_SPI_FLASH_STMICRO CONFIG_SUPPORT_RAW_INITRD CONFIG_SYS_ARCH_TIMER CONFIG_SYS_BOARD CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE CONFIG_SYS_DCACHE_OFF CONFIG_SYS_FDT_SAVE_ADDRESS CONFIG_SYS_FLASH_CFI CONFIG_SYS_FSL_ERRATUM_ESDHC135 CONFIG_SYS_HAS_SERDES CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_LITTLE_ENDIAN CONFIG_SYS_LOAD_ADDR CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR CONFIG_SYS_NS16550 CONFIG_SYS_PLLFIN CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_TIMER_SYS_TICK_CH CONFIG_USB_EHCI_FSL CONFIG_U_QE CONFIG_VERSION_VARIABLE Signed-off-by: Tom Rini <trini@konsulko.com>
100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#ifndef __PHYCORE_IMX8MP_H
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#define __PHYCORE_IMX8MP_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
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#define CONFIG_SYS_MONITOR_LEN SZ_512K
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_STACK 0x960000
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#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#define CONFIG_POWER_PCA9450
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"image=Image\0" \
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"console=ttymxc0,115200\0" \
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"fdt_addr=0x48000000\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"ip_dyn=yes\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"mmcroot=2\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi;\0 " \
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"nfsroot=/nfs\0" \
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"netargs=setenv bootargs console=${console} root=/dev/nfs ip=dhcp " \
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"nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi;\0" \
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x80000000
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/* UART */
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#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE SZ_2K
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* USDHC */
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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#endif /* __PHYCORE_IMX8MP_H */
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