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https://github.com/AsahiLinux/u-boot
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a0018fc820
Commit40686c394e("riscv: Clean up IPI initialization code") caused U-Boot failed to boot on SiFive HiFive Unleashed board. The codes inside arch_cpu_init_dm() may call U-Boot timer APIs before the call to riscv_init_ipi(). At that time the timer register base (e.g.: the SiFive CLINT device in this case) is unknown yet. It might be the name riscv_init_ipi() that misleads people to only consider it is related to IPI, but in fact the timer capability is provided by the same SiFive CLINT device that provides the IPI. Timer capability is needed for both UP and SMP. Considering that the original refactor does have benefits, that it makes the IPI code more similar to U-Boot initialization idioms. It also removes some quite ugly macros. Let's do the minimal revert instead of a complete revert, plus a fixes to arch_cpu_init_dm() to consider the SPL case. Fixes:40686c394e("riscv: Clean up IPI initialization code") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Leo Liang <ycliang@andestech.com>
122 lines
2.6 KiB
C
122 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <asm/encoding.h>
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#include <dm/uclass-internal.h>
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#include <linux/bitops.h>
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/*
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* The variables here must be stored in the data section since they are used
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* before the bss section is available.
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*/
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#ifdef CONFIG_OF_PRIOR_STAGE
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phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
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#endif
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#ifndef CONFIG_XIP
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u32 hart_lottery __attribute__((section(".data"))) = 0;
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/*
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* The main hart running U-Boot has acquired available_harts_lock until it has
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* finished initialization of global data.
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*/
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u32 available_harts_lock = 1;
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#endif
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static inline bool supports_extension(char ext)
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{
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#ifdef CONFIG_CPU
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struct udevice *dev;
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char desc[32];
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uclass_find_first_device(UCLASS_CPU, &dev);
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if (!dev) {
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debug("unable to find the RISC-V cpu device\n");
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return false;
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}
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if (!cpu_get_desc(dev, desc, sizeof(desc))) {
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/* skip the first 4 characters (rv32|rv64) */
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if (strchr(desc + 4, ext))
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return true;
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}
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return false;
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#else /* !CONFIG_CPU */
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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return csr_read(CSR_MISA) & (1 << (ext - 'a'));
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#else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
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#warning "There is no way to determine the available extensions in S-mode."
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#warning "Please convert your board to use the RISC-V CPU driver."
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return false;
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#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
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#endif /* CONFIG_CPU */
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}
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static int riscv_cpu_probe(void)
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{
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#ifdef CONFIG_CPU
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int ret;
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/* probe cpus so that RISC-V timer can be bound */
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ret = cpu_probe_all();
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if (ret)
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return log_msg_ret("RISC-V cpus probe failed\n", ret);
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#endif
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return 0;
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}
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int arch_cpu_init_dm(void)
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{
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int ret;
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ret = riscv_cpu_probe();
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if (ret)
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return ret;
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/* Enable FPU */
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if (supports_extension('d') || supports_extension('f')) {
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csr_set(MODE_PREFIX(status), MSTATUS_FS);
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csr_write(CSR_FCSR, 0);
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}
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if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
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/*
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* Enable perf counters for cycle, time,
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* and instret counters only
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*/
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#ifdef CONFIG_RISCV_PRIV_1_9
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csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
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csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
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#else
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csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
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#endif
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/* Disable paging */
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if (supports_extension('s'))
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#ifdef CONFIG_RISCV_PRIV_1_9
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csr_read_clear(CSR_MSTATUS, SR_VM);
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#else
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csr_write(CSR_SATP, 0);
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#endif
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}
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#if CONFIG_IS_ENABLED(SMP)
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ret = riscv_init_ipi();
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if (ret)
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return ret;
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#endif
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return 0;
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}
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int arch_early_init_r(void)
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{
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return riscv_cpu_probe();
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}
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