u-boot/arch/arm/cpu/armv7
Benoît Thébaudeau 323846561a mx5/6 clocks: Fix SDHC clocks
The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.

Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
2012-10-15 11:54:12 -07:00
..
am33xx SPL: Create arch/arm/lib/spl.c for board_init_f and jump_to_image_linux 2012-09-27 09:49:59 -07:00
exynos arm:exynos: Enable data cache at exynos based processors. 2012-09-01 14:58:24 +02:00
highbank arm: Remove additional config flags 2012-10-04 14:51:50 +02:00
mx5 mx5/6 clocks: Fix SDHC clocks 2012-10-15 11:54:12 -07:00
mx6 mx5/6: Define default SoC input clock frequencies 2012-10-15 11:54:10 -07:00
omap-common arm: Remove additional config flags 2012-10-04 14:51:50 +02:00
omap3 arm: armv7: omap3: Fix restore sequence in lowlevel_init 2012-10-08 11:15:04 -07:00
omap4 ARM: OMAP4/5: Move USB clocks to essential group. 2012-07-07 14:07:36 +02:00
omap5 ARM: OMAP4/5: Move USB clocks to essential group. 2012-07-07 14:07:36 +02:00
rmobile arm: rmobile: bugfix: wrong register saving in lowlevel_init 2012-10-08 11:15:04 -07:00
s5p-common arm/s5pxx: Fix get_timer_masked to get the time. 2012-09-01 14:58:23 +02:00
s5pc1xx armv7: add appropriate headers for assembly functions 2012-05-15 08:31:26 +02:00
socfpga ARM: Add Altera SOCFPGA Cyclone5 2012-10-04 18:11:52 +02:00
tegra-common Tegra20: Move some include files to arch-tegra for sharing with Tegra30 2012-10-15 11:54:06 -07:00
tegra20 Tegra20: Move some include files to arch-tegra for sharing with Tegra30 2012-10-15 11:54:06 -07:00
u8500 snowball: Adding board specific cache cleanup routine 2012-09-01 14:58:20 +02:00
zynq arm: Support new Xilinx Zynq platform 2012-10-04 16:46:29 +02:00
cache_v7.c armv7: cache: remove flush on un-aligned invalidate 2011-09-04 11:36:16 +02:00
config.mk ARM: prevent misaligned array inits 2012-10-15 11:53:07 -07:00
cpu.c arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0 2012-09-01 14:58:22 +02:00
lowlevel_init.S armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stack 2012-09-01 14:58:19 +02:00
Makefile tegra20: enable SPL for tegra20 boards 2012-09-01 14:58:22 +02:00
start.S armv7 cpu_init_crit: Simplify code 2012-10-04 14:19:07 +02:00
syslib.c ARMV7: Vexpress: fix build errors 2010-12-08 23:44:21 +01:00