mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 00:47:26 +00:00
d491dc09e4
This commit removes the programming sequence that enables PLLE and UPHY PLL hardware power sequencers. Per TRM, boot software should enable PLLE and UPHY PLLs in software controlled power-on state and should power down PLL before jumping into kernel or the next stage boot software. Adds call to board_cleanup_before_linux to facilitate this. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
25 lines
854 B
C
25 lines
854 B
C
#ifndef _TEGRA_XUSB_PADCTL_H_
|
|
#define _TEGRA_XUSB_PADCTL_H_
|
|
|
|
struct tegra_xusb_phy;
|
|
|
|
/**
|
|
* tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
|
|
* @type: the type of PHY to obtain
|
|
*
|
|
* The type of PHY varies between SoC generations. Typically there are XUSB,
|
|
* PCIe and SATA PHYs, though not all generations support all of them. The
|
|
* value of type can usually be directly parsed from a device tree.
|
|
*
|
|
* Return: a pointer to the PHY or NULL if no such PHY exists
|
|
*/
|
|
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
|
|
|
|
void tegra_xusb_padctl_init(void);
|
|
void tegra_xusb_padctl_exit(void);
|
|
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
|
|
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
|
|
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
|
|
int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
|
|
|
|
#endif
|