mirror of
https://github.com/AsahiLinux/u-boot
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1a73bd842e
With xip booting configuration, we don't need to copy the next image (U-Boot or linux xipimage) from flash to sdram area. Flash memory organization is like this: spl-U-Boot: u-boot-spl.bin : 0x0800_0000 U-Boot : u-boot-dtb.bin : 0x0800_8000 linux : xipImage : 0x0800_8000 It is also possible to have U-Boot binary & linux binaries configured at different addresses of flash memory like U-Boot at 0x0800_8000 & linux xipImage at 0x0800_4000. But in any case, spl-U-Boot needs to be compiled for U-Boot as next binary with SPL_OS_BOOT option disabled. By default, spl is configured to boot linux xipImage. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
169 lines
3.2 KiB
C
169 lines
3.2 KiB
C
/*
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* (C) Copyright 2016
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* Vikas Manocha, <vikas.manocha@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/fmc.h>
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#include <dm/platform_data/serial_stm32x7.h>
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#include <asm/arch/stm32_periph.h>
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#include <asm/arch/stm32_defs.h>
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#include <asm/arch/syscfg.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
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{
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int mr_node;
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mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
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if (mr_node < 0)
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return mr_node;
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*mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
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"reg", 0, mr_size, false);
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debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
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return 0;
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}
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int dram_init(void)
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{
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int rv;
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fdt_addr_t mr_base, mr_size;
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#ifndef CONFIG_SUPPORT_SPL
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struct udevice *dev;
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rv = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (rv) {
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debug("DRAM init failed: %d\n", rv);
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return rv;
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}
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#endif
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rv = get_memory_base_size(&mr_base, &mr_size);
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if (rv)
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return rv;
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gd->ram_size = mr_size;
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gd->ram_top = mr_base;
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return rv;
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}
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int dram_init_banksize(void)
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{
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fdt_addr_t mr_base, mr_size;
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get_memory_base_size(&mr_base, &mr_size);
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/*
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* Fill in global info with description of SRAM configuration
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*/
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gd->bd->bi_dram[0].start = mr_base;
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gd->bd->bi_dram[0].size = mr_size;
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return 0;
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}
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#ifdef CONFIG_ETH_DESIGNWARE
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static int stmmac_setup(void)
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{
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clock_setup(SYSCFG_CLOCK_CFG);
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/* Set >RMII mode */
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STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
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clock_setup(STMMAC_CLOCK_CFG);
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return 0;
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}
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int board_early_init_f(void)
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{
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stmmac_setup();
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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debug("SPL: booting kernel\n");
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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int spl_dram_init(void)
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{
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struct udevice *dev;
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int rv;
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rv = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (rv)
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debug("DRAM init failed: %d\n", rv);
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return rv;
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}
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void spl_board_init(void)
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{
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spl_dram_init();
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preloader_console_init();
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arch_cpu_init(); /* to configure mpu for sdram rw permissions */
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_XIP;
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}
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#endif
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u32 get_board_rev(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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struct gpio_desc gpio = {};
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int node;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
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if (node < 0)
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return -1;
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gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
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GPIOD_IS_OUT);
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if (dm_gpio_is_valid(&gpio)) {
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dm_gpio_set_value(&gpio, 0);
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mdelay(10);
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dm_gpio_set_value(&gpio, 1);
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}
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/* read button 1*/
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node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
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if (node < 0)
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return -1;
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gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
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&gpio, GPIOD_IS_IN);
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if (dm_gpio_is_valid(&gpio)) {
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if (dm_gpio_get_value(&gpio))
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puts("usr button is at HIGH LEVEL\n");
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else
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puts("usr button is at LOW LEVEL\n");
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}
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
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return 0;
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}
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