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b38dbd4622
should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005 |
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.. | ||
commproc.c | ||
config.mk | ||
cpu.c | ||
cpu_init.c | ||
ether_fcc.c | ||
i2c.c | ||
interrupts.c | ||
Makefile | ||
pci.c | ||
resetvec.S | ||
serial_scc.c | ||
spd_sdram.c | ||
speed.c | ||
start.S | ||
traps.c |