mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
03544c6640
The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
243 lines
6.6 KiB
C
243 lines
6.6 KiB
C
/*
|
|
*
|
|
* Congatec Conga-QEVAl board configuration file.
|
|
*
|
|
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
|
* Based on Freescale i.MX6Q Sabre Lite board configuration file.
|
|
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
|
* Leo Sartre, <lsartre@adeneo-embedded.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __CONFIG_CGTQMX6EVAL_H
|
|
#define __CONFIG_CGTQMX6EVAL_H
|
|
|
|
#include "mx6_common.h"
|
|
|
|
#define CONFIG_MACH_TYPE 4122
|
|
|
|
/* Size of malloc() pool */
|
|
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
|
|
|
#define CONFIG_BOARD_EARLY_INIT_F
|
|
#define CONFIG_MISC_INIT_R
|
|
|
|
#define CONFIG_MXC_UART
|
|
#define CONFIG_MXC_UART_BASE UART2_BASE
|
|
|
|
/* MMC Configs */
|
|
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
|
|
|
/* Miscellaneous commands */
|
|
#define CONFIG_CMD_BMODE
|
|
|
|
/* Thermal support */
|
|
#define CONFIG_IMX_THERMAL
|
|
|
|
/* I2C Configs */
|
|
#define CONFIG_CMD_I2C
|
|
#define CONFIG_SYS_I2C
|
|
#define CONFIG_SYS_I2C_MXC
|
|
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
|
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
|
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
|
#define CONFIG_SYS_I2C_SPEED 100000
|
|
|
|
/* PMIC */
|
|
#define CONFIG_POWER
|
|
#define CONFIG_POWER_I2C
|
|
#define CONFIG_POWER_PFUZE100
|
|
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
|
|
|
/* USB Configs */
|
|
#define CONFIG_CMD_USB
|
|
#define CONFIG_CMD_FAT
|
|
#define CONFIG_USB_EHCI
|
|
#define CONFIG_USB_EHCI_MX6
|
|
#define CONFIG_USB_STORAGE
|
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
|
#define CONFIG_USB_HOST_ETHER
|
|
#define CONFIG_USB_ETHER_ASIX
|
|
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
|
#define CONFIG_MXC_USB_FLAGS 0
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
|
|
#define CONFIG_USB_KEYBOARD
|
|
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
|
|
|
|
#define CONFIG_CI_UDC
|
|
#define CONFIG_USBD_HS
|
|
#define CONFIG_USB_GADGET_DUALSPEED
|
|
|
|
#define CONFIG_USB_GADGET
|
|
#define CONFIG_CMD_USB_MASS_STORAGE
|
|
#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
|
#define CONFIG_USB_GADGET_DOWNLOAD
|
|
#define CONFIG_USB_GADGET_VBUS_DRAW 2
|
|
|
|
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
|
|
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
|
|
#define CONFIG_G_DNL_MANUFACTURER "Congatec"
|
|
|
|
/* Framebuffer */
|
|
#define CONFIG_VIDEO
|
|
#define CONFIG_VIDEO_IPUV3
|
|
#define CONFIG_CFB_CONSOLE
|
|
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
|
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
|
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
|
#define CONFIG_VIDEO_BMP_RLE8
|
|
#define CONFIG_SPLASH_SCREEN
|
|
#define CONFIG_SPLASH_SCREEN_ALIGN
|
|
#define CONFIG_BMP_16BPP
|
|
#define CONFIG_VIDEO_LOGO
|
|
#define CONFIG_VIDEO_BMP_LOGO
|
|
#ifdef CONFIG_MX6DL
|
|
#define CONFIG_IPUV3_CLK 198000000
|
|
#else
|
|
#define CONFIG_IPUV3_CLK 264000000
|
|
#endif
|
|
#define CONFIG_IMX_HDMI
|
|
|
|
/* SATA */
|
|
#define CONFIG_CMD_SATA
|
|
#define CONFIG_DWC_AHSATA
|
|
#define CONFIG_SYS_SATA_MAX_DEVICE 1
|
|
#define CONFIG_DWC_AHSATA_PORT_ID 0
|
|
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
|
|
#define CONFIG_LBA48
|
|
#define CONFIG_LIBATA
|
|
|
|
/* Ethernet */
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_DHCP
|
|
#define CONFIG_CMD_MII
|
|
#define CONFIG_FEC_MXC
|
|
#define CONFIG_MII
|
|
#define IMX_FEC_BASE ENET_BASE_ADDR
|
|
#define CONFIG_FEC_XCV_TYPE RGMII
|
|
#define CONFIG_ETHPRIME "FEC"
|
|
#define CONFIG_FEC_MXC_PHYADDR 6
|
|
#define CONFIG_PHYLIB
|
|
#define CONFIG_PHY_ATHEROS
|
|
|
|
/* Command definition */
|
|
|
|
#define CONFIG_MXC_UART_BASE UART2_BASE
|
|
#define CONFIG_CONSOLE_DEV "ttymxc1"
|
|
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
|
|
#define CONFIG_SYS_MMC_ENV_DEV 0
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"script=boot.scr\0" \
|
|
"image=zImage\0" \
|
|
"fdtfile=imx6q-qmx6.dtb\0" \
|
|
"fdt_addr_r=0x18000000\0" \
|
|
"boot_fdt=try\0" \
|
|
"ip_dyn=yes\0" \
|
|
"console=" CONFIG_CONSOLE_DEV "\0" \
|
|
"bootm_size=0x10000000\0" \
|
|
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
|
"mmcpart=1\0" \
|
|
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
|
"update_sd_firmware=" \
|
|
"if test ${ip_dyn} = yes; then " \
|
|
"setenv get_cmd dhcp; " \
|
|
"else " \
|
|
"setenv get_cmd tftp; " \
|
|
"fi; " \
|
|
"if mmc dev ${mmcdev}; then " \
|
|
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
|
"setexpr fw_sz ${filesize} / 0x200; " \
|
|
"setexpr fw_sz ${fw_sz} + 1; " \
|
|
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
|
"fi; " \
|
|
"fi\0" \
|
|
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
|
"root=${mmcroot}\0" \
|
|
"loadbootscript=" \
|
|
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
|
"bootscript=echo Running bootscript from mmc ...; " \
|
|
"source\0" \
|
|
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
|
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
|
|
"mmcboot=echo Booting from mmc ...; " \
|
|
"run mmcargs; " \
|
|
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
|
"if run loadfdt; then " \
|
|
"bootz ${loadaddr} - ${fdt_addr_r}; " \
|
|
"else " \
|
|
"if test ${boot_fdt} = try; then " \
|
|
"bootz; " \
|
|
"else " \
|
|
"echo WARN: Cannot load the DT; " \
|
|
"fi; " \
|
|
"fi; " \
|
|
"else " \
|
|
"bootz; " \
|
|
"fi;\0" \
|
|
"netargs=setenv bootargs console=${console},${baudrate} " \
|
|
"root=/dev/nfs " \
|
|
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
|
"netboot=echo Booting from net ...; " \
|
|
"run netargs; " \
|
|
"if test ${ip_dyn} = yes; then " \
|
|
"setenv get_cmd dhcp; " \
|
|
"else " \
|
|
"setenv get_cmd tftp; " \
|
|
"fi; " \
|
|
"${get_cmd} ${image}; " \
|
|
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
|
"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
|
|
"bootz ${loadaddr} - ${fdt_addr_r}; " \
|
|
"else " \
|
|
"if test ${boot_fdt} = try; then " \
|
|
"bootz; " \
|
|
"else " \
|
|
"echo WARN: Cannot load the DT; " \
|
|
"fi; " \
|
|
"fi; " \
|
|
"else " \
|
|
"bootz; " \
|
|
"fi;\0" \
|
|
|
|
#define CONFIG_BOOTCOMMAND \
|
|
"mmc dev ${mmcdev};" \
|
|
"if mmc rescan; then " \
|
|
"if run loadbootscript; then " \
|
|
"run bootscript; " \
|
|
"else " \
|
|
"if run loadimage; then " \
|
|
"run mmcboot; " \
|
|
"else run netboot; " \
|
|
"fi; " \
|
|
"fi; " \
|
|
"else run netboot; fi"
|
|
|
|
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
|
#define CONFIG_SYS_MEMTEST_END 0x10010000
|
|
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
|
|
|
|
/* Physical Memory Map */
|
|
#define CONFIG_NR_DRAM_BANKS 1
|
|
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
|
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
|
|
|
|
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
|
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
|
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
|
|
|
#define CONFIG_SYS_INIT_SP_OFFSET \
|
|
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
|
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
|
|
|
/* Environment organization */
|
|
#define CONFIG_ENV_SIZE (8 * 1024)
|
|
|
|
#define CONFIG_ENV_IS_IN_MMC
|
|
|
|
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
|
#define CONFIG_SYS_MMC_ENV_DEV 0
|
|
|
|
#endif /* __CONFIG_CGTQMX6EVAL_H */
|