mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 19:02:12 +00:00
90496afc27
Allows to change clock frequency of debug uart, thus supporting wide range of baudrates. Enable / disable functionality is not implemented yet. In most use cases of SDM845 (i.e. mobile phones and tablets) it's not needed, because qualcomm first stage bootloader leaves it initialized, and on the other hand there's no possibility to replace signed first stage bootloader with u-boot. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com>
46 lines
1 KiB
C
46 lines
1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Qualcomm APQ8016, APQ8096, SDM845
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*
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* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*/
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#ifndef _CLOCK_SNAPDRAGON_H
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#define _CLOCK_SNAPDRAGON_H
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#define CFG_CLK_SRC_CXO (0 << 8)
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#define CFG_CLK_SRC_GPLL0 (1 << 8)
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#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
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#define CFG_CLK_SRC_MASK (7 << 8)
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struct pll_vote_clk {
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uintptr_t status;
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int status_bit;
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uintptr_t ena_vote;
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int vote_bit;
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};
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struct vote_clk {
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uintptr_t cbcr_reg;
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uintptr_t ena_vote;
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int vote_bit;
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};
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struct bcr_regs {
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uintptr_t cfg_rcgr;
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uintptr_t cmd_rcgr;
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uintptr_t M;
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uintptr_t N;
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uintptr_t D;
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};
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struct msm_clk_priv {
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phys_addr_t base;
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};
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void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
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void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
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void clk_enable_cbc(phys_addr_t cbcr);
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void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
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void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
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int div, int m, int n, int source);
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#endif
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