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https://github.com/AsahiLinux/u-boot
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ef509b9063
k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
69 lines
2.4 KiB
C
69 lines
2.4 KiB
C
/*
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* Keystone2: DDR3 initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
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{
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unsigned int tmp;
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while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
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& 0x00000001) != 0x00000001)
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;
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__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
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tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
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tmp &= ~(phy_cfg->pgcr1_mask);
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tmp |= phy_cfg->pgcr1_val;
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__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
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__raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
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__raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
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__raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
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__raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
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tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
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tmp &= ~(phy_cfg->dcr_mask);
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tmp |= phy_cfg->dcr_val;
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__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
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__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
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__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
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__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
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__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
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__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
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__raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
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__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
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__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
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__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
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__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
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__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
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__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
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while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
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;
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__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
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while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
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;
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}
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void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
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{
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__raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
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__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
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__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
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__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
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__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
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__raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
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__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
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}
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