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a615dfda8c
Do maintain a 200 usecs period of stable power and clock before asserting the CKE signal and sending commands, have at least 200 DRAM clock cycles pass after initialization before data access. Signed-off-by: Anatolij Gustschin <agust@denx.de>
172 lines
6.2 KiB
C
172 lines
6.2 KiB
C
/*
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* (C) Copyright 2007-2009 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/mpc512x.h>
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/*
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* MDDRC Config Runtime Settings
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*/
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ddr512x_config_t default_mddrc_config = {
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.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG,
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.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
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.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
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.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
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};
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u32 default_init_seq[] = {
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_MICRON_INIT_DEV_OP,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_EM2,
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CONFIG_SYS_DDRCMD_NOP,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_EM2,
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CONFIG_SYS_DDRCMD_EM3,
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CONFIG_SYS_DDRCMD_EN_DLL,
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CONFIG_SYS_MICRON_INIT_DEV_OP,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_RFSH,
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CONFIG_SYS_MICRON_INIT_DEV_OP,
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CONFIG_SYS_DDRCMD_OCD_DEFAULT,
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CONFIG_SYS_DDRCMD_PCHG_ALL,
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CONFIG_SYS_DDRCMD_NOP
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};
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/*
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* fixed sdram init:
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* The board doesn't use memory modules that have serial presence
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* detect or similar mechanism for discovery of the DRAM settings
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*/
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long int fixed_sdram(ddr512x_config_t *mddrc_config,
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u32 *dram_init_seq, int seq_sz)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
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u32 msize_log2 = __ilog2(msize);
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u32 i;
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/* take default settings and init sequence if necessary */
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if (mddrc_config == NULL)
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mddrc_config = &default_mddrc_config;
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if (dram_init_seq == NULL) {
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dram_init_seq = default_init_seq;
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seq_sz = sizeof(default_init_seq)/sizeof(u32);
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}
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/* Initialize IO Control */
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out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
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/* Initialize DDR Local Window */
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out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
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out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
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sync_law(&im->sysconf.ddrlaw.ar);
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/* DDR Enable */
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/*
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* the "enable" combination: DRAM controller out of reset,
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* clock enabled, command mode -- BUT leave CKE low for now
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*/
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i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK;
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out_be32(&im->mddrc.ddr_sys_config, i);
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/* maintain 200 microseconds of stable power and clock */
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udelay(200);
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/* apply a NOP, it shouldn't harm */
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP);
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/* now assert CKE (high) */
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i |= MDDRC_SYS_CFG_CKE_MASK;
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out_be32(&im->mddrc.ddr_sys_config, i);
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/* Initialize DDR Priority Manager */
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out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
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out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
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out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
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out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
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out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
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out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
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out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
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out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
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out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
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out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
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out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
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out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
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out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
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out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
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out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
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out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
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out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
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out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
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out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
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out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
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out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
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out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
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out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
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/*
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* Initialize MDDRC
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* put MDDRC in CMD mode and
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* set the max time between refreshes to 0 during init process
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*/
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out_be32(&im->mddrc.ddr_sys_config,
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mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
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out_be32(&im->mddrc.ddr_time_config0,
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mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
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out_be32(&im->mddrc.ddr_time_config1,
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mddrc_config->ddr_time_config1);
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out_be32(&im->mddrc.ddr_time_config2,
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mddrc_config->ddr_time_config2);
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/* Initialize DDR with either default or supplied init sequence */
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for (i = 0; i < seq_sz; i++)
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out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
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/* Start MDDRC */
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out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
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out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
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/* Allow for the DLL to startup before accessing data */
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udelay(10);
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msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
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/* Fix DDR Local Window for new size */
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out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
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sync_law(&im->sysconf.ddrlaw.ar);
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return msize;
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}
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