mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/printk.h>
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#include "ddrphy-init.h"
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#include "ddrphy-regs.h"
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enum dram_freq {
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DRAM_FREQ_1333M,
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DRAM_FREQ_1600M,
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DRAM_FREQ_NR,
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};
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static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
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static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
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static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
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static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
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static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
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static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
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static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
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static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
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static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
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int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
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{
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enum dram_freq freq_e;
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u32 tmp;
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switch (freq) {
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case 1333:
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freq_e = DRAM_FREQ_1333M;
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break;
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case 1600:
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freq_e = DRAM_FREQ_1600M;
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break;
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default:
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pr_err("unsupported DRAM frequency %d MHz\n", freq);
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return -EINVAL;
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}
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writel(0x0300c473, phy_base + PHY_PGCR1);
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writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
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writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
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writel(0x00083DEF, phy_base + PHY_PTR2);
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writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
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writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
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writel(0xF004001A, phy_base + PHY_DSGCR);
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/* change the value of the on-die pull-up/pull-down registors */
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tmp = readl(phy_base + PHY_DXCCR);
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tmp &= ~0x0ee0;
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tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
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writel(tmp, phy_base + PHY_DXCCR);
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writel(0x0000040B, phy_base + PHY_DCR);
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writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
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writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
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writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
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writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
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writel(0x00000006, phy_base + PHY_MR1);
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writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
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writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
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while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
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;
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writel(0x0300C473, phy_base + PHY_PGCR1);
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writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
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return 0;
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}
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