mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 00:47:26 +00:00
a09fea1d28
- In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
399 lines
11 KiB
C
399 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
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*/
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/*
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* mpc8313epb board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1
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#define CONFIG_SPL_INIT_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
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#define CONFIG_SPL_MAX_SIZE (4 * 1024)
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#define CONFIG_SPL_PAD_TO 0x4000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
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#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
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#endif
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#ifndef CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_FSL_ELBC 1
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/*
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* On-board devices
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*
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* TSEC1 is VSC switch
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* TSEC2 is SoC TSEC
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*/
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#define CONFIG_VSC7385_ENET
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#define CONFIG_TSEC2
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#if !defined(CONFIG_SPL_BUILD)
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#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00001000
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#define CONFIG_SYS_MEMTEST_END 0x07f00000
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/* Early revs of this board will lock up hard when attempting
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* to access the PMC registers, unless a JTAG debugger is
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* connected, or some resistor modifications are made.
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*/
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#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
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/*
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* Device configurations
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*/
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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#define CONFIG_TSEC1
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/* The flash address and size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE 0xFE7FE000
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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/*
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* Manually set up DDR parameters, as this board does not
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* seem to have the SPD connected to I2C.
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*/
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#define CONFIG_SYS_DDR_SIZE 128 /* MB */
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_RD_NEVER \
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| CSCONFIG_ODT_WR_ONLY_CURRENT \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10)
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/* 0x80010102 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00220802 */
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#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (10 << TIMING_CFG1_REFREC_SHIFT) \
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| (3 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x3835a322 */
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (5 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x129048c6 */ /* P9-45,may need tuning */
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#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x05100500 */
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#if defined(CONFIG_DDR_2T_TIMING)
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#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_DBW_32 \
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| SDRAM_CFG_2T_EN)
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/* 0x43088000 */
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#else
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#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_DBW_32)
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/* 0x43080000 */
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#endif
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#define CONFIG_SYS_SDRAM_CFG2 0x00401000
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/* set burst length to 8 for 32-bit data path */
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#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
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| (0x0632 << SDRAM_MODE_SD_SHIFT))
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/* 0x44480632 */
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#define CONFIG_SYS_DDR_MODE_2 0x8000C000
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#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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/*0x02000000*/
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
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| DDRCDR_PZ_NOMZ \
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| DDRCDR_NZ_NOMZ \
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| DDRCDR_M_ODR)
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
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#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
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!defined(CONFIG_SPL_BUILD)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/* drivers/mtd/nand/raw/nand.c */
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#if defined(CONFIG_SPL_BUILD)
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#define CONFIG_SYS_NAND_BASE 0xFFF00000
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#else
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#define CONFIG_SYS_NAND_BASE 0xE2800000
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#endif
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#define CONFIG_MTD_PARTITION
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
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#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
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/* Still needed for spl_minimal.c */
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#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
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#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
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/* local bus write LED / read status buffer (BCSR) mapping */
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#define CONFIG_SYS_BCSR_ADDR 0xFA000000
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#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
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/* map at 0xFA000000 on LCS3 */
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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/* VSC7385 Base address on LCS2 */
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#define CONFIG_SYS_VSC7385_BASE 0xF0000000
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#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
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#endif
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#define CONFIG_MPC83XX_GPIO 1
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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/*
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* TSEC
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*/
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#define CONFIG_GMII /* MII PHY management */
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x1c
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC1_PHYIDX 0
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#endif
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#ifdef CONFIG_TSEC2
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define TSEC2_PHY_ADDR 4
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC2_PHYIDX 0
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#endif
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC1"
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/*
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* Environment
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*/
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#define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
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/* System IO Config */
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#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
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/* Enable Internal USB Phy and GPIO on LCD Connector */
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#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_NETDEV "eth1"
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#define CONFIG_HOSTNAME "mpc8313erdb"
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#define CONFIG_ROOTPATH "/nfs/root/path"
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#define CONFIG_BOOTFILE "uImage"
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/* U-Boot image on TFTP server */
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#define CONFIG_UBOOTPATH "u-boot.bin"
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#define CONFIG_FDTFILE "mpc8313erdb.dtb"
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 800000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=" CONFIG_NETDEV "\0" \
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"ethprime=TSEC1\0" \
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"uboot=" CONFIG_UBOOTPATH "\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +$filesize; " \
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"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
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" $filesize; " \
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"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
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" +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
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" $filesize\0" \
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"fdtaddr=780000\0" \
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"fdtfile=" CONFIG_FDTFILE "\0" \
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"console=ttyS0\0" \
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"setbootargs=setenv bootargs " \
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"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
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"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
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"$netdev:off " \
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"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv rootdev /dev/nfs;" \
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"run setbootargs;" \
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"run setipargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv rootdev /dev/ram;" \
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"run setbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#endif /* __CONFIG_H */
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