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https://github.com/AsahiLinux/u-boot
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323 lines
9.3 KiB
C
323 lines
9.3 KiB
C
/*
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* (C) Copyright 2008
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* Based on board/amcc/yosemite/yosemite.c
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* info for FLASH chips */
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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int board_early_init_f(void)
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{
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register uint reg;
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/*
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* Setup the external bus controller/chip selects
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*/
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mfebc(xbcfg, reg);
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mtebc(xbcfg, reg | 0x04000000); /* Set ATC */
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/*
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* Setup the GPIO pins
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*/
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/* setup Address lines for flash size 64Meg. */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
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/* setup emac */
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
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out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
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/* UART0 and UART1*/
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000);
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out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000);
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
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out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
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/* disable boot-eeprom WP */
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out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
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out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
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out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
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out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
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out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
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/* external interrupts IRQ0...3 */
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out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
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out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
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out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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/*
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* Setup other serial configuration
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*/
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mfsdr(sdr_pci0, reg);
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mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
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mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
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mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
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return 0;
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}
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int misc_init_r(void)
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{
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uint pbcr;
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int size_val;
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uint sz;
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/* Re-do sizing to get full correct info */
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mfebc(pb0cr, pbcr);
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if (gd->bd->bi_flashsize > 0x08000000)
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panic("Max. flash banksize is 128 MB!\n");
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for (sz = gd->bd->bi_flashsize, size_val = 7;
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((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
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sz <<= 1;
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtebc(pb0cr, pbcr);
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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/*
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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*/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long addr;
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/*
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* Set priority for all PLB3 devices to 0.
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* Set PLB3 arbiter to fair mode.
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*/
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mfsdr(sdr_amp1, addr);
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mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb3_acr);
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mtdcr(plb3_acr, addr | 0x80000000);
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/*
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* Set priority for all PLB4 devices to 0.
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*/
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mfsdr(sdr_amp0, addr);
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mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
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mtdcr(plb4_acr, addr);
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/*
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* Set Nebula PLB4 arbiter to fair mode.
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*/
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/* Segment0 */
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addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
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addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
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addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
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addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
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mtdcr(plb0_acr, addr);
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/* Segment1 */
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addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
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addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
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addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
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addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
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mtdcr(plb1_acr, addr);
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/* enable 66 MHz ext. Clock */
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out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
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out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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/*
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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*/
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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/*
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* Set up Direct MMIO registers
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*/
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/*
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* PowerPC440 EP PCI Master configuration.
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* Map one 1Gig range of PLB/processor addresses to PCI memory space.
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* PLB address 0xA0000000-0xDFFFFFFF
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* ==> PCI address 0xA0000000-0xDFFFFFFF
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* Use byte reversed out routines to handle endianess.
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* Make this region non-prefetchable.
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*/
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out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */
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out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
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out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
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out32r(PCIX0_PMM0PCIHA, 0x00000000);
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out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
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out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */
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out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
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out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
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out32r(PCIX0_PMM1PCIHA, 0x00000000);
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out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
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out32r(PCIX0_PTM1MS, 0x00000001);
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out32r(PCIX0_PTM1LA, 0);
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out32r(PCIX0_PTM2MS, 0);
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out32r(PCIX0_PTM2LA, 0);
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/*
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* Set up Configuration registers
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*/
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/* Program the board's subsystem id/vendor id */
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pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
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CONFIG_SYS_PCI_SUBSYS_VENDORID);
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pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
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/* Configure command register as bus master */
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pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* 240nS PCI clock */
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pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
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/* No error reporting */
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pci_write_config_word(0, PCI_ERREN, 0);
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pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
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/*
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* pci_master_init
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*
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*/
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
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void pci_master_init(struct pci_controller *hose)
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{
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unsigned short temp_short;
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/*
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* Write the PowerPC440 EP PCI Configuration regs.
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* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
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* Enable PowerPC440 EP to act as a PCI memory target (PTM).
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*/
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pci_read_config_word(0, PCI_COMMAND, &temp_short);
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pci_write_config_word(0, PCI_COMMAND,
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temp_short | PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
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/*
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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*/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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