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The watchdog timer is part of the sl28cpld management controller. The watchdog timer usually supervises the bootloader boot-up and if it bites the failsafe bootloader will be activated. Apart from that it supports the usual board level reset and one SMARC speciality: driving the WDT_TIMEOUT# signal. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
194 lines
6.1 KiB
ReStructuredText
194 lines
6.1 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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Kontron SMARC-sAL28
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===================
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The Kontron SMARC-sAL28 board is a TSN-enabled dual-core ARM A72
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processor module with an on-chip 6-port TSN switch and a 3D GPU.
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Quickstart
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----------
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Compile U-Boot
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^^^^^^^^^^^^^^
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Configure and compile the binary::
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$ make kontron_sl28_defconfig
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$ CROSS_COMPILE=aarch64-linux-gnu make
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Copy u-boot.rom to a TFTP server.
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Install the bootloader on the board
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Please note, this bootloader doesn't support the builtin watchdog (yet),
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therefore you have to disable it, see below. Otherwise you'll end up in
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the failsafe bootloader on every reset::
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> tftp path/to/u-boot.rom
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> sf probe 0
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> sf update $fileaddr 0x210000 $filesize
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The board is fully failsafe, you can't break anything. But because you've
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disabled the builtin watchdog you might have to manually enter failsafe
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mode by asserting the ``FORCE_RECOV#`` line during board reset.
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Update image
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------------
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After the build finished, there will be an update image called
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u-boot.update. This can either be used in the DFU mode (which isn't
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supported yet) or encapsulated in an EFI UpdateCapsule.
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To build the capsule use the following command
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$ tools/mkeficapsule -f u-boot.update -i 1 UpdateUboot
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Afterward you can copy this file to your ESP into the /EFI/UpdateCapsule/
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folder. On the next EFI boot this will automatically update your
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bootloader.
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Useful I2C tricks
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-----------------
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The board has a board management controller which is not supported in
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u-boot (yet). But you can use the i2c command to access it.
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- reset into failsafe bootloader::
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> i2c mw 4a 5.1 0; i2c mw 4a 6.1 6b; i2c mw 4a 4.1 42
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- read board management controller version::
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> i2c md 4a 3.1 1
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Builtin watchdog
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----------------
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The builtin watchdog will supervise the bootloader startup. If anything
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goes wrong it will reset the board and boot into the failsafe bootloader.
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Once the bootloader is started successfully, it will disable the watchdog
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timer.
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wdt command flags
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^^^^^^^^^^^^^^^^^
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The `wdt start` as well as the `wdt expire` command take a flags argument.
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The supported bitmask is as follows.
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| Bit | Description |
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| --- | ----------------------------- |
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| 0 | Enable failsafe mode |
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| 1 | Lock the control register |
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| 2 | Disable board reset |
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| 3 | Enable WDT_TIME_OUT# line |
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For example, you can use `wdt expire 1` to issue a reset and boot into the
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failsafe bootloader.
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Disable the builtin watchdog
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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If for some reason, this isn't a desired behavior, the watchdog can also
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be configured to not be enabled on board reset. It's configuration is saved
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in the non-volatile board configuration bits. To change these you can use
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the `sl28 nvm` command.
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For more information on the non-volatile board configuration bits, see the
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following section.
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Non-volatile Board Configuration Bits
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-------------------------------------
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The board has 16 configuration bits which are stored in the CPLD and are
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non-volatile. These can be changed by the `sl28 nvm` command.
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=== ===============================================================
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Bit Description
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=== ===============================================================
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0 Power-on inhibit
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1 Enable eMMC boot
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2 Enable watchdog by default
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3 Disable failsafe watchdog by default
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4 Clock generator selection bit 0
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5 Clock generator selection bit 1
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6 Disable CPU SerDes clock #2 and PCIe-A clock output
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7 Disable PCIe-B and PCIe-C clock output
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8 Keep onboard PHYs in reset
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9 Keep USB hub in reset
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10 Keep eDP-to-LVDS converter in reset
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11 Enable I2C stuck recovery on I2C PM and I2C GP busses
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12 Enable automatic onboard PHY H/W reset
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13 reserved
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14 Used by the RCW to determine boot source
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15 Used by the RCW to determine boot source
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=== ===============================================================
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Please note, that if the board is in failsafe mode, the bits will have the
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factory defaults, ie. all bits are off.
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Power-On Inhibit
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^^^^^^^^^^^^^^^^
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If this is set, the board doesn't automatically turn on when power is
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applied. Instead, the user has to either toggle the ``PWR_BTN#`` line or
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use any other wake-up source such as RTC alarm or Wake-on-LAN.
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eMMC Boot
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^^^^^^^^^
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If this is set, the RCW will be fetched from the on-board eMMC at offset
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1MiB. For further details, have a look at the `Reset Configuration Word
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Documentation`_.
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Watchdog
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^^^^^^^^
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By default, the CPLD watchdog is enabled in failsafe mode. Using bits 2 and
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3, the user can change its mode or disable it altogether.
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===== ===== ===============================
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Bit 2 Bit 3 Description
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===== ===== ===============================
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0 0 Watchdog enabled, failsafe mode
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0 1 Watchdog disabled
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1 0 Watchdog enabled, failsafe mode
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1 1 Watchdog enabled, normal mode
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===== ===== ===============================
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Clock Generator Select
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^^^^^^^^^^^^^^^^^^^^^^
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The board is prepared to supply different SerDes clock speeds. But for now,
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only setting 0 is supported, otherwise the CPU will hang because the PLL
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will not lock.
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Clock Output Disable And Keep Devices In Reset
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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To safe power, the user might disable different devices and clock output of
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the board. It is not supported to disable the "CPU SerDes clock #2" for
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now, otherwise the CPU will hang because the PLL will not lock.
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Automatic reset of the onboard PHYs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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By default, there is no hardware reset of the onboard PHY. This is because
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for Wake-on-LAN, some registers have to retain their values. If you don't
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use the WOL feature and a soft reset of the PHY is not enough you can
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enable the hardware reset. The onboard PHY hardware reset follows the
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power-on reset.
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Further documentation
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---------------------
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- `Vendor Documentation`_
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- `Reset Configuration Word Documentation`_
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.. _Reset Configuration Word Documentation: https://raw.githubusercontent.com/kontron/rcw-smarc-sal28/master/README.md
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.. _Vendor Documentation: https://raw.githubusercontent.com/kontron/u-boot-smarc-sal28/master/board/kontron/sl28/README.md
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