mirror of
https://github.com/AsahiLinux/u-boot
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f5bc9929a2
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM. Add arch core support for it. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
157 lines
4.5 KiB
C
157 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/ioc_rk3588.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FIREWALL_DDR_BASE 0xfe030000
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#define FW_DDR_MST5_REG 0x54
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#define FW_DDR_MST13_REG 0x74
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#define FW_DDR_MST21_REG 0x94
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#define FW_DDR_MST26_REG 0xa8
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#define FW_DDR_MST27_REG 0xac
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#define FIREWALL_SYSMEM_BASE 0xfe038000
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#define FW_SYSM_MST5_REG 0x54
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#define FW_SYSM_MST13_REG 0x74
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#define FW_SYSM_MST21_REG 0x94
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#define FW_SYSM_MST26_REG 0xa8
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#define FW_SYSM_MST27_REG 0xac
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#define PMU1_IOC_BASE 0xfd5f0000
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#define PMU2_IOC_BASE 0xfd5f4000
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#define BUS_IOC_BASE 0xfd5f8000
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#define BUS_IOC_GPIO2A_IOMUX_SEL_L 0x40
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#define BUS_IOC_GPIO2B_IOMUX_SEL_L 0x48
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#define BUS_IOC_GPIO2D_IOMUX_SEL_L 0x58
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#define BUS_IOC_GPIO2D_IOMUX_SEL_H 0x5c
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#define BUS_IOC_GPIO3A_IOMUX_SEL_L 0x60
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static struct mm_region rk3588_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xf0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf0000000UL,
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.phys = 0xf0000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x900000000,
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.phys = 0x900000000,
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.size = 0x150000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3588_mem_map;
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/* GPIO0B_IOMUX_SEL_H */
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enum {
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GPIO0B5_SHIFT = 4,
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GPIO0B5_MASK = GENMASK(7, 4),
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GPIO0B5_REFER = 8,
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GPIO0B5_UART2_TX_M0 = 10,
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GPIO0B6_SHIFT = 8,
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GPIO0B6_MASK = GENMASK(11, 8),
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GPIO0B6_REFER = 8,
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GPIO0B6_UART2_RX_M0 = 10,
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};
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void board_debug_uart_init(void)
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{
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__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void *)BUS_IOC_BASE;
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static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
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/* Refer to BUS_IOC */
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rk_clrsetreg(&pmu2_ioc->gpio0b_iomux_sel_h,
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GPIO0B6_MASK | GPIO0B5_MASK,
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GPIO0B6_REFER << GPIO0B6_SHIFT |
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GPIO0B5_REFER << GPIO0B5_SHIFT);
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/* UART2_M0 Switch iomux */
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rk_clrsetreg(&bus_ioc->gpio0b_iomux_sel_h,
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GPIO0B6_MASK | GPIO0B5_MASK,
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GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
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GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
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}
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#ifdef CONFIG_SPL_BUILD
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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if (reg & 0x1)
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return;
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asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
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writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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}
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#endif
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#ifndef CONFIG_TPL_BUILD
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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int secure_reg;
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/* Set the SDMMC eMMC crypto_ns FSPI access secure area */
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG);
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secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
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secure_reg &= 0xffff0000;
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writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST27_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST5_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST13_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST21_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
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secure_reg &= 0xffff;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST26_REG);
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secure_reg = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
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secure_reg &= 0xffff0000;
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writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
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#endif
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return 0;
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}
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#endif
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