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c3dc39a2f8
It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
338 lines
5.4 KiB
C
338 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd
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*/
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#ifndef _ASM_ARCH_SDRAM_RK3036_H
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#define _ASM_ARCH_SDRAM_RK3036_H
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struct rk3036_ddr_pctl {
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u32 scfg;
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u32 sctl;
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u32 stat;
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u32 intrstat;
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u32 reserved0[12];
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u32 mcmd;
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u32 powctl;
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u32 powstat;
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u32 cmdtstat;
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u32 cmdtstaten;
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u32 reserved1[3];
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u32 mrrcfg0;
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u32 mrrstat0;
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u32 mrrstat1;
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u32 reserved2[4];
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u32 mcfg1;
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u32 mcfg;
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u32 ppcfg;
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u32 mstat;
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u32 lpddr2zqcfg;
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u32 reserved3;
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u32 dtupdes;
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u32 dtuna;
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u32 dtune;
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u32 dtuprd0;
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u32 dtuprd1;
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u32 dtuprd2;
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u32 dtuprd3;
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u32 dtuawdt;
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u32 reserved4[3];
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 reserved5[47];
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u32 dtuwactl;
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u32 dturactl;
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u32 dtucfg;
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u32 dtuectl;
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u32 dtuwd0;
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u32 dtuwd1;
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u32 dtuwd2;
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u32 dtuwd3;
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u32 dtuwdm;
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u32 dturd0;
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u32 dturd1;
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u32 dturd2;
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u32 dturd3;
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u32 dtulfsrwd;
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u32 dtulfsrrd;
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u32 dtueaf;
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u32 dfitctrldelay;
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u32 dfiodtcfg;
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u32 dfiodtcfg1;
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u32 dfiodtrankmap;
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u32 dfitphywrdata;
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u32 dfitphywrlat;
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u32 reserved7[2];
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u32 dfitrddataen;
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u32 dfitphyrdlat;
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u32 reserved8[2];
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u32 dfitphyupdtype0;
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u32 dfitphyupdtype1;
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u32 dfitphyupdtype2;
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u32 dfitphyupdtype3;
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u32 dfitctrlupdmin;
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u32 dfitctrlupdmax;
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u32 dfitctrlupddly;
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u32 reserved9;
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u32 dfiupdcfg;
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u32 dfitrefmski;
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u32 dfitctrlupdi;
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u32 reserved10[4];
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u32 dfitrcfg0;
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u32 dfitrstat0;
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u32 dfitrwrlvlen;
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u32 dfitrrdlvlen;
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u32 dfitrrdlvlgateen;
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u32 dfiststat0;
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u32 dfistcfg0;
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u32 dfistcfg1;
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u32 reserved11;
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u32 dfitdramclken;
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u32 dfitdramclkdis;
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u32 dfistcfg2;
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u32 dfistparclr;
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u32 dfistparlog;
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u32 reserved12[3];
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u32 dfilpcfg0;
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u32 reserved13[3];
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u32 dfitrwrlvlresp0;
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u32 dfitrwrlvlresp1;
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u32 dfitrwrlvlresp2;
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u32 dfitrrdlvlresp0;
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u32 dfitrrdlvlresp1;
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u32 dfitrrdlvlresp2;
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u32 dfitrwrlvldelay0;
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u32 dfitrwrlvldelay1;
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u32 dfitrwrlvldelay2;
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u32 dfitrrdlvldelay0;
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u32 dfitrrdlvldelay1;
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u32 dfitrrdlvldelay2;
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u32 dfitrrdlvlgatedelay0;
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u32 dfitrrdlvlgatedelay1;
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u32 dfitrrdlvlgatedelay2;
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u32 dfitrcmd;
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u32 reserved14[46];
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u32 ipvr;
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u32 iptr;
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};
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check_member(rk3036_ddr_pctl, iptr, 0x03fc);
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struct rk3036_ddr_phy {
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u32 ddrphy_reg1;
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u32 ddrphy_reg3;
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u32 ddrphy_reg2;
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u32 reserve[11];
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u32 ddrphy_reg4a;
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u32 ddrphy_reg4b;
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u32 reserve1[5];
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u32 ddrphy_reg16;
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u32 reserve2;
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u32 ddrphy_reg18;
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u32 ddrphy_reg19;
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u32 reserve3;
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u32 ddrphy_reg21;
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u32 reserve4;
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u32 ddrphy_reg22;
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u32 reserve5[3];
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u32 ddrphy_reg25;
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u32 ddrphy_reg26;
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u32 ddrphy_reg27;
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u32 ddrphy_reg28;
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u32 reserve6[17];
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u32 ddrphy_reg6;
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u32 ddrphy_reg7;
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u32 reserve7;
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u32 ddrphy_reg8;
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u32 ddrphy_reg0e4;
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u32 reserve8[11];
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u32 ddrphy_reg9;
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u32 ddrphy_reg10;
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u32 reserve9;
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u32 ddrphy_reg11;
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u32 ddrphy_reg124;
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u32 reserve10[38];
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u32 ddrphy_reg29;
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u32 reserve11[40];
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u32 ddrphy_reg264;
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u32 reserve12[18];
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u32 ddrphy_reg2a;
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u32 reserve13[4];
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u32 ddrphy_reg30;
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u32 ddrphy_reg31;
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u32 ddrphy_reg32;
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u32 ddrphy_reg33;
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u32 ddrphy_reg34;
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u32 ddrphy_reg35;
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u32 ddrphy_reg36;
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u32 ddrphy_reg37;
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u32 ddrphy_reg38;
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u32 ddrphy_reg39;
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u32 ddrphy_reg40;
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u32 ddrphy_reg41;
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u32 ddrphy_reg42;
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u32 ddrphy_reg43;
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u32 ddrphy_reg44;
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u32 ddrphy_reg45;
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u32 ddrphy_reg46;
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u32 ddrphy_reg47;
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u32 ddrphy_reg48;
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u32 ddrphy_reg49;
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u32 ddrphy_reg50;
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u32 ddrphy_reg51;
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u32 ddrphy_reg52;
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u32 ddrphy_reg53;
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u32 reserve14;
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u32 ddrphy_reg54;
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u32 ddrphy_reg55;
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u32 ddrphy_reg56;
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u32 ddrphy_reg57;
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u32 ddrphy_reg58;
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u32 ddrphy_reg59;
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u32 ddrphy_reg5a;
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u32 ddrphy_reg5b;
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u32 ddrphy_reg5c;
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u32 ddrphy_reg5d;
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u32 ddrphy_reg5e;
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u32 reserve15[28];
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u32 ddrphy_reg5f;
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u32 reserve16[6];
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u32 ddrphy_reg60;
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u32 ddrphy_reg61;
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u32 ddrphy_reg62;
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};
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check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8);
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struct rk3036_pctl_timing {
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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};
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struct rk3036_phy_timing {
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u32 mr[4];
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u32 bl;
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u32 cl_al;
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};
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typedef union {
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u32 noc_timing;
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struct {
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u32 acttoact:6;
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u32 rdtomiss:6;
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u32 wrtomiss:6;
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u32 burstlen:3;
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u32 rdtowr:5;
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u32 wrtord:5;
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u32 bwratio:1;
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};
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} rk3036_noc_timing;
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struct rk3036_ddr_timing {
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u32 freq;
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struct rk3036_pctl_timing pctl_timing;
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struct rk3036_phy_timing phy_timing;
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rk3036_noc_timing noc_timing;
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};
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struct rk3036_service_sys {
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u32 id_coreid;
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u32 id_revisionid;
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u32 ddrconf;
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u32 ddrtiming;
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u32 ddrmode;
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u32 readlatency;
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};
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struct rk3036_ddr_config {
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/*
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* 000: lpddr
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* 001: ddr
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* 010: ddr2
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* 011: ddr3
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* 100: lpddr2-s2
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* 101: lpddr2-s4
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* 110: lpddr3
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*/
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u32 ddr_type;
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u32 rank;
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u32 cs0_row;
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u32 cs1_row;
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/* 2: 4bank, 3: 8bank */
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u32 bank;
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u32 col;
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/* bw(0: 8bit, 1: 16bit, 2: 32bit) */
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u32 bw;
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};
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/* rk3036 sdram initial */
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void sdram_init(void);
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/* get ddr die config, implement in specific board */
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void get_ddr_config(struct rk3036_ddr_config *config);
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/* get ddr size on board */
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size_t sdram_size(void);
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#endif
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