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https://github.com/AsahiLinux/u-boot
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5ab30c3176
Add full ddr pctl registers and bit masks for px30. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
239 lines
7.2 KiB
C
239 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd
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*/
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#ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H
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#define _ASM_ARCH_SDRAM_PCTL_PX30_H
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#include <asm/arch-rockchip/sdram_common.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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struct ddr_pctl_regs {
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u32 pctl[35][2];
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};
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/* ddr pctl registers define */
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#define DDR_PCTL2_MSTR 0x0
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#define DDR_PCTL2_STAT 0x4
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#define DDR_PCTL2_MSTR1 0x8
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#define DDR_PCTL2_MRCTRL0 0x10
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#define DDR_PCTL2_MRCTRL1 0x14
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#define DDR_PCTL2_MRSTAT 0x18
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#define DDR_PCTL2_MRCTRL2 0x1c
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#define DDR_PCTL2_DERATEEN 0x20
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#define DDR_PCTL2_DERATEINT 0x24
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#define DDR_PCTL2_MSTR2 0x28
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#define DDR_PCTL2_PWRCTL 0x30
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#define DDR_PCTL2_PWRTMG 0x34
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#define DDR_PCTL2_HWLPCTL 0x38
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#define DDR_PCTL2_RFSHCTL0 0x50
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#define DDR_PCTL2_RFSHCTL1 0x54
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#define DDR_PCTL2_RFSHCTL2 0x58
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#define DDR_PCTL2_RFSHCTL4 0x5c
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#define DDR_PCTL2_RFSHCTL3 0x60
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#define DDR_PCTL2_RFSHTMG 0x64
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#define DDR_PCTL2_RFSHTMG1 0x68
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#define DDR_PCTL2_RFSHCTL5 0x6c
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#define DDR_PCTL2_INIT0 0xd0
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#define DDR_PCTL2_INIT1 0xd4
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#define DDR_PCTL2_INIT2 0xd8
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#define DDR_PCTL2_INIT3 0xdc
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#define DDR_PCTL2_INIT4 0xe0
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#define DDR_PCTL2_INIT5 0xe4
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#define DDR_PCTL2_INIT6 0xe8
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#define DDR_PCTL2_INIT7 0xec
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#define DDR_PCTL2_DIMMCTL 0xf0
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#define DDR_PCTL2_RANKCTL 0xf4
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#define DDR_PCTL2_CHCTL 0xfc
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#define DDR_PCTL2_DRAMTMG0 0x100
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#define DDR_PCTL2_DRAMTMG1 0x104
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#define DDR_PCTL2_DRAMTMG2 0x108
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#define DDR_PCTL2_DRAMTMG3 0x10c
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#define DDR_PCTL2_DRAMTMG4 0x110
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#define DDR_PCTL2_DRAMTMG5 0x114
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#define DDR_PCTL2_DRAMTMG6 0x118
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#define DDR_PCTL2_DRAMTMG7 0x11c
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#define DDR_PCTL2_DRAMTMG8 0x120
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#define DDR_PCTL2_DRAMTMG9 0x124
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#define DDR_PCTL2_DRAMTMG10 0x128
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#define DDR_PCTL2_DRAMTMG11 0x12c
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#define DDR_PCTL2_DRAMTMG12 0x130
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#define DDR_PCTL2_DRAMTMG13 0x134
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#define DDR_PCTL2_DRAMTMG14 0x138
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#define DDR_PCTL2_DRAMTMG15 0x13c
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#define DDR_PCTL2_DRAMTMG16 0x140
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#define DDR_PCTL2_ZQCTL0 0x180
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#define DDR_PCTL2_ZQCTL1 0x184
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#define DDR_PCTL2_ZQCTL2 0x188
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#define DDR_PCTL2_ZQSTAT 0x18c
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#define DDR_PCTL2_DFITMG0 0x190
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#define DDR_PCTL2_DFITMG1 0x194
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#define DDR_PCTL2_DFILPCFG0 0x198
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#define DDR_PCTL2_DFILPCFG1 0x19c
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#define DDR_PCTL2_DFIUPD0 0x1a0
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#define DDR_PCTL2_DFIUPD1 0x1a4
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#define DDR_PCTL2_DFIUPD2 0x1a8
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#define DDR_PCTL2_DFIMISC 0x1b0
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#define DDR_PCTL2_DFITMG2 0x1b4
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#define DDR_PCTL2_DFITMG3 0x1b8
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#define DDR_PCTL2_DFISTAT 0x1bc
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#define DDR_PCTL2_DBICTL 0x1c0
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#define DDR_PCTL2_ADDRMAP0 0x200
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#define DDR_PCTL2_ADDRMAP1 0x204
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#define DDR_PCTL2_ADDRMAP2 0x208
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#define DDR_PCTL2_ADDRMAP3 0x20c
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#define DDR_PCTL2_ADDRMAP4 0x210
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#define DDR_PCTL2_ADDRMAP5 0x214
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#define DDR_PCTL2_ADDRMAP6 0x218
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#define DDR_PCTL2_ADDRMAP7 0x21c
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#define DDR_PCTL2_ADDRMAP8 0x220
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#define DDR_PCTL2_ADDRMAP9 0x224
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#define DDR_PCTL2_ADDRMAP10 0x228
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#define DDR_PCTL2_ADDRMAP11 0x22c
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#define DDR_PCTL2_ODTCFG 0x240
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#define DDR_PCTL2_ODTMAP 0x244
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#define DDR_PCTL2_SCHED 0x250
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#define DDR_PCTL2_SCHED1 0x254
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#define DDR_PCTL2_PERFHPR1 0x25c
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#define DDR_PCTL2_PERFLPR1 0x264
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#define DDR_PCTL2_PERFWR1 0x26c
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#define DDR_PCTL2_DQMAP0 0x280
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#define DDR_PCTL2_DQMAP1 0x284
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#define DDR_PCTL2_DQMAP2 0x288
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#define DDR_PCTL2_DQMAP3 0x28c
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#define DDR_PCTL2_DQMAP4 0x290
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#define DDR_PCTL2_DQMAP5 0x294
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#define DDR_PCTL2_DBG0 0x300
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#define DDR_PCTL2_DBG1 0x304
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#define DDR_PCTL2_DBGCAM 0x308
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#define DDR_PCTL2_DBGCMD 0x30c
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#define DDR_PCTL2_DBGSTAT 0x310
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#define DDR_PCTL2_SWCTL 0x320
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#define DDR_PCTL2_SWSTAT 0x324
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#define DDR_PCTL2_POISONCFG 0x36c
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#define DDR_PCTL2_POISONSTAT 0x370
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#define DDR_PCTL2_ADVECCINDEX 0x374
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#define DDR_PCTL2_ADVECCSTAT 0x378
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#define DDR_PCTL2_PSTAT 0x3fc
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#define DDR_PCTL2_PCCFG 0x400
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#define DDR_PCTL2_PCFGR_n 0x404
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#define DDR_PCTL2_PCFGW_n 0x408
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#define DDR_PCTL2_PCTRL_n 0x490
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#define UMCTL2_REGS_FREQ(n) \
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((0x1000 * (n) + (((n) > 0) ? 0x1000 : 0)))
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/* PCTL2_MSTR */
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#define PCTL2_FREQUENCY_MODE_MASK (1)
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#define PCTL2_FREQUENCY_MODE_SHIFT (29)
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#define PCTL2_DLL_OFF_MODE BIT(15)
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/* PCTL2_STAT */
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#define PCTL2_SELFREF_TYPE_MASK (3 << 4)
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#define PCTL2_SELFREF_TYPE_SR_NOT_AUTO (2 << 4)
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#define PCTL2_OPERATING_MODE_MASK (7)
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#define PCTL2_OPERATING_MODE_INIT (0)
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#define PCTL2_OPERATING_MODE_NORMAL (1)
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#define PCTL2_OPERATING_MODE_PD (2)
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#define PCTL2_OPERATING_MODE_SR (3)
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/* PCTL2_MRCTRL0 */
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#define PCTL2_MR_WR BIT(31)
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#define PCTL2_MR_ADDR_SHIFT (12)
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#define PCTL2_MR_RANK_SHIFT (4)
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#define PCTL2_MR_TYPE_WR (0)
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#define PCTL2_MR_TYPE_RD (1)
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/* PCTL2_MRCTRL1 */
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#define PCTL2_MR_ADDRESS_SHIFT (8)
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#define PCTL2_MR_DATA_MASK (0xff)
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/* PCTL2_MRSTAT */
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#define PCTL2_MR_WR_BUSY BIT(0)
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/* PCTL2_DERATEEN */
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#define PCTL2_DERATE_ENABLE (1)
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/* PCTL2_PWRCTL */
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#define PCTL2_SELFREF_SW BIT(5)
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#define PCTL2_POWERDOWN_EN BIT(1)
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#define PCTL2_SELFREF_EN (1)
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/* PCTL2_PWRTMG */
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#define PCTL2_SELFREF_TO_X32_MASK (0xFF)
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#define PCTL2_SELFREF_TO_X32_SHIFT (16)
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#define PCTL2_POWERDOWN_TO_X32_MASK (0x1F)
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/* PCTL2_INIT3 */
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#define PCTL2_DDR34_MR0_SHIFT (16)
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#define PCTL2_LPDDR234_MR1_SHIFT (16)
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#define PCTL2_DDR34_MR1_SHIFT (0)
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#define PCTL2_LPDDR234_MR2_SHIFT (0)
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/* PCTL2_INIT4 */
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#define PCTL2_DDR34_MR2_SHIFT (16)
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#define PCTL2_LPDDR234_MR3_SHIFT (16)
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#define PCTL2_DDR34_MR3_SHIFT (0)
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#define PCTL2_LPDDR4_MR13_SHIFT (0)
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/* PCTL2_INIT6 */
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#define PCTL2_DDR4_MR4_SHIFT (16)
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#define PCTL2_LPDDR4_MR11_SHIFT (16)
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#define PCTL2_DDR4_MR5_SHIFT (0)
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#define PCTL2_LPDDR4_MR12_SHIFT (0)
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/* PCTL2_INIT7 */
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#define PCTL2_LPDDR4_MR22_SHIFT (16)
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#define PCTL2_DDR4_MR6_SHIFT (0)
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#define PCTL2_LPDDR4_MR14_SHIFT (0)
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#define PCTL2_MR_MASK (0xffff)
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/* PCTL2_RFSHCTL3 */
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#define PCTL2_DIS_AUTO_REFRESH (1)
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/* PCTL2_ZQCTL0 */
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#define PCTL2_DIS_AUTO_ZQ BIT(31)
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#define PCTL2_DIS_SRX_ZQCL BIT(30)
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/* PCTL2_DFILPCFG0 */
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#define PCTL2_DFI_LP_EN_SR BIT(8)
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#define PCTL2_DFI_LP_EN_SR_MASK BIT(8)
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#define PCTL2_DFI_LP_EN_SR_SHIFT (8)
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/* PCTL2_DFIMISC */
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#define PCTL2_DFI_INIT_COMPLETE_EN (1)
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/* PCTL2_DFISTAT */
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#define PCTL2_DFI_LP_ACK BIT(1)
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#define PCTL2_DFI_INIT_COMPLETE (1)
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/* PCTL2_DBG1 */
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#define PCTL2_DIS_HIF BIT(1)
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/* PCTL2_DBGCAM */
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#define PCTL2_DBG_WR_Q_EMPTY BIT(26)
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#define PCTL2_DBG_RD_Q_EMPTY BIT(25)
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#define PCTL2_DBG_LPR_Q_DEPTH_MASK (0xffff << 8)
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#define PCTL2_DBG_LPR_Q_DEPTH_EMPTY (0x0 << 8)
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/* PCTL2_DBGCMD */
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#define PCTL2_RANK1_REFRESH BIT(1)
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#define PCTL2_RANK0_REFRESH (1)
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/* PCTL2_DBGSTAT */
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#define PCTL2_RANK1_REFRESH_BUSY BIT(1)
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#define PCTL2_RANK0_REFRESH_BUSY (1)
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/* PCTL2_SWCTL */
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#define PCTL2_SW_DONE (1)
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#define PCTL2_SW_DONE_CLEAR (0)
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/* PCTL2_SWSTAT */
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#define PCTL2_SW_DONE_ACK (1)
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/* PCTL2_PSTAT */
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#define PCTL2_WR_PORT_BUSY_0 BIT(16)
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#define PCTL2_RD_PORT_BUSY_0 (1)
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/* PCTL2_PCTRLn */
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#define PCTL2_PORT_EN (1)
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void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
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int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
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u32 dramtype);
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int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
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u32 dramtype);
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u32 pctl_dis_zqcs_aref(void __iomem *pctl_base);
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void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq);
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u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
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struct sdram_cap_info *cap_info,
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u32 dram_type);
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int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
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u32 sr_idle, u32 pd_idle);
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#endif
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