mirror of
https://github.com/AsahiLinux/u-boot
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e869b3485c
Add DDR driver for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
356 lines
10 KiB
C
356 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd
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*/
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#ifndef _ASM_ARCH_SDRAM_COMMON_H
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#define _ASM_ARCH_SDRAM_COMMON_H
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#ifndef MHZ
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#define MHZ (1000 * 1000)
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#endif
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#define PATTERN (0x5aa5f00f)
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#define MIN(a, b) (((a) > (b)) ? (b) : (a))
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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/* get head info for initial */
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#define DDR_FREQ_F0_SHIFT (0)
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#define DDR_FREQ_F1_SHIFT (12)
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#define DDR_FREQ_F2_SHIFT (0)
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#define DDR_FREQ_F3_SHIFT (12)
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#define DDR_FREQ_F4_SHIFT (0)
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#define DDR_FREQ_F5_SHIFT (12)
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#define DDR_FREQ_MASK (0xfff)
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#define UART_INFO_ID_SHIFT (28)
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#define UART_INFO_IOMUX_SHIFT (24)
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#define UART_INFO_BAUD_SHIFT (0)
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#define UART_INFO_ID(n) (((n) >> 28) & 0xf)
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#define UART_INFO_IOMUX(n) (((n) >> 24) & 0xf)
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#define UART_INFO_BAUD(n) ((n) & 0xffffff)
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/* g_ch_info[15:0]: g_stdby_idle */
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#define STANDBY_IDLE(n) ((n) & 0xffff)
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#define SR_INFO(n) (((n) >> 16) & 0xffff)
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#define PD_INFO(n) ((n) & 0xffff)
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#define FIRST_SCAN_CH(n) (((n) >> 28) & 0xf)
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#define CHANNEL_MASK(n) (((n) >> 24) & 0xf)
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#define STRIDE_TYPE(n) (((n) >> 16) & 0xff)
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#define DDR_2T_INFO(n) ((n) & 1)
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#define PLL_SSMOD_SPREAD(n) (((n) >> 1) & 0xff)
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#define PLL_SSMOD_DIV(n) (((n) >> 9) & 0xff)
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#define PLL_SSMOD_DOWNSPREAD(n) (((n) >> 17) & 0x3)
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/* sdram_head_info_v2 define */
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/* for *_drv_odten and *_drv_odtoff */
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#define PHY_DQ_DRV_SHIFT 0
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#define PHY_CA_DRV_SHIFT 8
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#define PHY_CLK_DRV_SHIFT 16
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#define DRAM_DQ_DRV_SHIFT 24
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#define DRV_INFO_PHY_DQ_DRV(n) ((n) & 0xff)
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#define DRV_INFO_PHY_CA_DRV(n) (((n) >> PHY_CA_DRV_SHIFT) & 0xff)
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#define DRV_INFO_PHY_CLK_DRV(n) (((n) >> PHY_CLK_DRV_SHIFT) & 0xff)
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#define DRV_INFO_DRAM_DQ_DRV(n) (((n) >> DRAM_DQ_DRV_SHIFT) & 0xff)
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/* for *_odt_info */
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#define DRAM_ODT_SHIFT 0
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#define PHY_ODT_SHIFT 8
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#define PHY_ODT_PUUP_EN_SHIFT 18
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#define PHY_ODT_PUDN_EN_SHIFT 19
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#define ODT_INFO_DRAM_ODT(n) (((n) >> DRAM_ODT_SHIFT) & 0xff)
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#define ODT_INFO_PHY_ODT(n) (((n) >> PHY_ODT_SHIFT) & 0x3ff)
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#define ODT_INFO_PULLUP_EN(n) (((n) >> PHY_ODT_PUUP_EN_SHIFT) & 1)
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#define ODT_INFO_PULLDOWN_EN(n) (((n) >> PHY_ODT_PUDN_EN_SHIFT) & 1)
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/* for *odt_en_freq; */
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#define DRAM_ODT_EN_FREQ_SHIFT 0
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#define PHY_ODT_EN_FREQ_SHIFT 12
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#define DRAMODT_EN_FREQ(n) (((n) >> DRAM_ODT_EN_FREQ_SHIFT) & \
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0xfff)
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#define PHYODT_EN_FREQ(n) (((n) >> PHY_ODT_EN_FREQ_SHIFT) & 0xfff)
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#define PHY_DQ_SR_SHIFT 0
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#define PHY_CA_SR_SHIFT 8
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#define PHY_CLK_SR_SHIFT 16
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#define DQ_SR_INFO(n) (((n) >> PHY_DQ_SR_SHIFT) & 0xff)
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#define CA_SR_INFO(n) (((n) >> PHY_CA_SR_SHIFT) & 0xff)
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#define CLK_SR_INFO(n) (((n) >> PHY_CLK_SR_SHIFT) & 0xff)
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/* LP4 */
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#define LP4_CA_ODT_SHIFT (18)
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#define LP4_DRV_PU_CAL_ODTEN_SHIFT (26)
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#define LP4_DRV_PU_CAL_ODTOFF_SHIFT (27)
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#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT (28)
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#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT (29)
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#define ODT_INFO_LP4_CA_ODT(n) (((n) >> LP4_CA_ODT_SHIFT) & \
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0xff)
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#define LP4_DRV_PU_CAL_ODTEN(n) \
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(((n) >> LP4_DRV_PU_CAL_ODTEN_SHIFT) & 1)
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#define LP4_DRV_PU_CAL_ODTOFF(n) \
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(((n) >> LP4_DRV_PU_CAL_ODTOFF_SHIFT) & 1)
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#define PHY_LP4_DRV_PULLDOWN_EN_ODTEN(n) \
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(((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTEN_SHIFT) & 1)
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#define PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(n) \
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(((n) >> PHY_LP4_DRV_PULLDOWN_EN_ODTOFF_SHIFT) & 1)
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#define PHY_LP4_CS_DRV_ODTEN_SHIFT (0)
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#define PHY_LP4_CS_DRV_ODTOFF_SHIFT (8)
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#define LP4_ODTE_CK_SHIFT (16)
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#define LP4_ODTE_CS_EN_SHIFT (17)
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#define LP4_ODTD_CA_EN_SHIFT (18)
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#define PHY_LP4_CS_DRV_ODTEN(n) \
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(((n) >> PHY_LP4_CS_DRV_ODTEN_SHIFT) & 0xff)
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#define PHY_LP4_CS_DRV_ODTOFF(n) \
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(((n) >> PHY_LP4_CS_DRV_ODTOFF_SHIFT) & 0xff)
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#define LP4_ODTE_CK_EN(n) (((n) >> LP4_ODTE_CK_SHIFT) & 1)
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#define LP4_ODTE_CS_EN(n) (((n) >> LP4_ODTE_CS_EN_SHIFT) & 1)
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#define LP4_ODTD_CA_EN(n) (((n) >> LP4_ODTD_CA_EN_SHIFT) & 1)
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#define PHY_LP4_DQ_VREF_SHIFT (0)
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#define LP4_DQ_VREF_SHIFT (10)
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#define LP4_CA_VREF_SHIFT (20)
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#define PHY_LP4_DQ_VREF(n) \
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(((n) >> PHY_LP4_DQ_VREF_SHIFT) & 0x3ff)
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#define LP4_DQ_VREF(n) (((n) >> LP4_DQ_VREF_SHIFT) & 0x3ff)
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#define LP4_CA_VREF(n) (((n) >> LP4_CA_VREF_SHIFT) & 0x3ff)
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#define LP4_DQ_ODT_EN_FREQ_SHIFT (0)
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#define PHY_LP4_ODT_EN_FREQ_SHIFT (12)
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#define LP4_CA_ODT_EN_FREQ_SHIFT (0)
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#define PHY_LP4_ODT_EN_FREQ(n) \
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(((n) >> PHY_LP4_ODT_EN_FREQ_SHIFT) & 0xfff)
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#define LP4_DQ_ODT_EN_FREQ(n) \
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(((n) >> LP4_DQ_ODT_EN_FREQ_SHIFT) & 0xfff)
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#define LP4_CA_ODT_EN_FREQ(n) \
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(((n) >> LP4_CA_ODT_EN_FREQ_SHIFT) & 0xfff)
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struct sdram_head_info_v0 {
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u32 start_tag;
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u32 version_info;
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u32 gcpu_gen_freq;
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u32 g_d2_lp2_freq;
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u32 g_d3_lp3_freq;
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u32 g_d4_lp4_freq;
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u32 g_uart_info;
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u32 g_sr_pd_idle;
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u32 g_ch_info;
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u32 g_2t_info;
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u32 reserved11;
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u32 reserved12;
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u32 reserved13;
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};
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struct index_info {
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u8 offset;
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u8 size;
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};
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struct sdram_head_info_index_v2 {
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u32 start_tag;
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u32 version_info;
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struct index_info cpu_gen_index;
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struct index_info global_index;
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struct index_info ddr2_index;
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struct index_info ddr3_index;
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struct index_info ddr4_index;
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struct index_info ddr5_index;
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struct index_info lp2_index;
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struct index_info lp3_index;
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struct index_info lp4_index;
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struct index_info lp5_index;
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struct index_info skew_index;
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struct index_info dq_map_index;
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struct index_info lp4x_index;
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struct index_info reserved;
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};
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struct global_info {
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u32 uart_info;
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u32 sr_pd_info;
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u32 ch_info;
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u32 info_2t;
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u32 reserved[4];
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};
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struct ddr2_3_4_lp2_3_info {
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u32 ddr_freq0_1;
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u32 ddr_freq2_3;
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u32 ddr_freq4_5;
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u32 drv_when_odten;
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u32 drv_when_odtoff;
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u32 odt_info;
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u32 odten_freq;
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u32 sr_when_odten;
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u32 sr_when_odtoff;
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};
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struct lp4_info {
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u32 ddr_freq0_1;
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u32 ddr_freq2_3;
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u32 ddr_freq4_5;
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u32 drv_when_odten;
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u32 drv_when_odtoff;
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u32 odt_info;
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u32 dq_odten_freq;
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u32 sr_when_odten;
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u32 sr_when_odtoff;
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u32 ca_odten_freq;
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u32 cs_drv_ca_odt_info;
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u32 vref_when_odten;
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u32 vref_when_odtoff;
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};
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struct dq_map_info {
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u32 byte_map[2];
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u32 lp3_dq0_7_map;
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u32 lp2_dq0_7_map;
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u32 ddr4_dq_map[4];
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};
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struct sdram_cap_info {
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unsigned int rank;
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/* dram column number, 0 means this channel is invalid */
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unsigned int col;
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/* dram bank number, 3:8bank, 2:4bank */
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unsigned int bk;
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/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned int bw;
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/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
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unsigned int dbw;
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/*
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* row_3_4 = 1: 6Gb or 12Gb die
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* row_3_4 = 0: normal die, power of 2
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*/
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unsigned int row_3_4;
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unsigned int cs0_row;
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unsigned int cs1_row;
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unsigned int cs0_high16bit_row;
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unsigned int cs1_high16bit_row;
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unsigned int ddrconfig;
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};
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struct sdram_base_params {
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unsigned int ddr_freq;
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unsigned int dramtype;
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unsigned int num_channels;
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unsigned int stride;
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unsigned int odt;
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};
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#define DDR_SYS_REG_VERSION (0x2)
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/* for modify tRFC and related timing */
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#define DIE_CAP_512MBIT 64
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#define DIE_CAP_1GBIT 128
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#define DIE_CAP_2GBIT 256
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#define DIE_CAP_4GBIT 512
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#define DIE_CAP_8GBIT 1024
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#define DIE_CAP_16GBIT 2048
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#define DIE_CAP_32GBIT 4096
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/*
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* sys_reg2 bitfield struct
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* [31] row_3_4_ch1
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* [30] row_3_4_ch0
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* [29:28] chinfo
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* [27] rank_ch1
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* [26:25] col_ch1
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* [24] bk_ch1
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* [23:22] cs0_row_ch1
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* [21:20] cs1_row_ch1
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* [19:18] bw_ch1
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* [17:16] dbw_ch1;
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* [15:13] ddrtype
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* [12] channelnum
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* [11] rank_ch0
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* [10:9] col_ch0
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* [8] bk_ch0
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* [7:6] cs0_row_ch0
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* [5:4] cs1_row_ch0
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* [3:2] bw_ch0
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* [1:0] dbw_ch0
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*/
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#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
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#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
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#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
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#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
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#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
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#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
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#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
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#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16)))
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#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1))
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#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16)))
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#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3))
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#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
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(8 + ((ch) * 16)))
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#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1))
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#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16)))
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#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3))
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#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
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#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3))
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/* sys reg 3 */
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#define SYS_REG_ENC_VERSION(n) ((n) << 28)
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#define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf)
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#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
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(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
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(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
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(5 + 2 * (ch)); \
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} while (0)
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#define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \
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((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \
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((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12)
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#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
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(os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
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(os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
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(os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
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(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
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(4 + 2 * (ch)); \
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} while (0)
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#define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \
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((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \
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((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12)
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#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch)))
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#define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3))
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void sdram_print_dram_type(unsigned char dramtype);
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void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base, u32 split);
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void sdram_print_stride(unsigned int stride);
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void sdram_org_config(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base,
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u32 *p_os_reg2, u32 *p_os_reg3, u32 channel);
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int sdram_detect_bw(struct sdram_cap_info *cap_info);
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int sdram_detect_cs(struct sdram_cap_info *cap_info);
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int sdram_detect_col(struct sdram_cap_info *cap_info,
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u32 coltmp);
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int sdram_detect_bank(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp);
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int sdram_detect_bg(struct sdram_cap_info *cap_info,
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u32 coltmp);
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int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type);
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int sdram_detect_row(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp, u32 rowtmp);
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int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp);
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int sdram_detect_high_row(struct sdram_cap_info *cap_info);
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int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type);
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u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type);
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void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n);
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#endif
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