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https://github.com/AsahiLinux/u-boot
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bde73b14f0
Newer DRAM initialization blobs from vendor can encode sdram info in a
new version 3 format. The new format makes use of more bits in sys_reg3
compared to the version 2 format.
Add basic support for detecting the version 3 format and decoding the
high bits used for ddrtype.
This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.
Details on the new format was deciphered from vendor u-boot commit [1].
[1] c69667e0e2
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _ASM_ARCH_SDRAM_H
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#define _ASM_ARCH_SDRAM_H
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enum {
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DDR4 = 0,
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DDR3 = 3,
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LPDDR2 = 5,
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LPDDR3 = 6,
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LPDDR4 = 7,
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LPDDR4X = 8,
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LPDDR5 = 9,
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DDR5 = 10,
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UNUSED = 0xFF
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};
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/*
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* sys_reg2 bitfield struct
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* [31] row_3_4_ch1
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* [30] row_3_4_ch0
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* [29:28] chinfo
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* [27] rank_ch1
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* [26:25] cs0_col_ch1
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* [24] bk_ch1
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* [23:22] low bits of cs0_row_ch1
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* [21:20] low bits of cs1_row_ch1
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* [19:18] bw_ch1
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* [17:16] dbw_ch1
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* [15:13] low bits of ddrtype
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* [12] channelnum
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* [11] low bit of rank_ch0
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* [10:9] cs0_col_ch0
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* [8] bk_ch0
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* [7:6] low bits of cs0_row_ch0
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* [5:4] low bits of cs1_row_ch0
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* [3:2] bw_ch0
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* [1:0] dbw_ch0
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*/
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#define SYS_REG_DDRTYPE_SHIFT 13
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#define SYS_REG_DDRTYPE_MASK 7
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#define SYS_REG_NUM_CH_SHIFT 12
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#define SYS_REG_NUM_CH_MASK 1
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#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
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#define SYS_REG_ROW_3_4_MASK 1
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#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
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#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
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#define SYS_REG_RANK_MASK 1
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#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
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#define SYS_REG_COL_MASK 3
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#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
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#define SYS_REG_BK_MASK 1
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#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
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#define SYS_REG_CS0_ROW_MASK 3
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#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
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#define SYS_REG_CS1_ROW_MASK 3
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#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
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#define SYS_REG_BW_MASK 3
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#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
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#define SYS_REG_DBW_MASK 3
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/*
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* sys_reg3 bitfield struct
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* [31:28] version
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* [16] cs3_delta_row
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* [15] cs2_delta_row
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* [14] high bit of rank_ch0
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* [13:12] high bits of ddrtype
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* [7] high bit of cs0_row_ch1
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* [6] high bit of cs1_row_ch1
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* [5] high bit of cs0_row_ch0
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* [4] high bit of cs1_row_ch0
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* [3:2] cs1_col_ch1
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* [1:0] cs1_col_ch0
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*/
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#define SYS_REG_VERSION_SHIFT 28
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#define SYS_REG_VERSION_MASK 0xf
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#define SYS_REG_EXTEND_DDRTYPE_SHIFT 12
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#define SYS_REG_EXTEND_DDRTYPE_MASK 3
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#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2)
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#define SYS_REG_EXTEND_CS0_ROW_MASK 1
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#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) (4 + (ch) * 2)
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#define SYS_REG_EXTEND_CS1_ROW_MASK 1
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#define SYS_REG_CS1_COL_SHIFT(ch) (0 + (ch) * 2)
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#define SYS_REG_CS1_COL_MASK 3
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/* Get sdram size decode from reg */
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size_t rockchip_sdram_size(phys_addr_t reg);
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/* Called by U-Boot board_init_r for Rockchip SoCs */
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int dram_init(void);
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#endif
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