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https://github.com/AsahiLinux/u-boot
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337bc26f05
The NPCM driver can use on npcm7xx/npcm8xx so add npcm8xx header for driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
93 lines
2.8 KiB
C
93 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_OTP_H_
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#define _NPCM_OTP_H_
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#ifdef CONFIG_ARCH_NPCM8XX
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enum {
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NPCM_KEY_SA = 0,
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NPCM_FUSE_SA = 0,
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NPCM_NUM_OF_SA = 1
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};
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#else
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enum {
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NPCM_KEY_SA = 0,
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NPCM_FUSE_SA = 1,
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NPCM_NUM_OF_SA = 2
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};
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#endif
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/* arrray images in flash, to program during fisrt boot (offsets in sector) */
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#define SA_KEYS_FLASH_IMAGE_OFFSET (0x000)
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#define SA_FUSE_FLASH_IMAGE_OFFSET (0x400)
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#define SA_TAG_FLASH_IMAGE_OFFSET (0x800)
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/* F U S E I M G S */
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#define SA_TAG_FLASH_IMAGE_VAL {0x46, 0x55, 0x53, 0x45, 0x49, 0x4d, 0x47, 0x53}
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#define SA_TAG_FLASH_IMAGE_SIZE (8)
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#define SA_FUSE_FUSTRAP_OFFSET (0x00)
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#define SA_FUSE_FUSTRAP_OSECBOOT_MASK (0x00800000)
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struct npcm_otp_regs {
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unsigned int fst;
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unsigned int faddr;
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unsigned int fdata;
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unsigned int fcfg;
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unsigned int fustrap_fkeyind;
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unsigned int fctl;
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};
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#define FST_RDY BIT(0)
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#define FST_RDST BIT(1)
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#define FST_RIEN BIT(2)
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#ifdef CONFIG_ARCH_NPCM8XX
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#define FADDR_BYTEADDR(addr) ((addr) << 3)
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#define FADDR_BITPOS(pos) ((pos) << 0)
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#define FADDR_VAL(addr, pos) (FADDR_BITPOS(pos) | FADDR_BYTEADDR(addr))
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#define FADDR_IN_PROG BIT(16)
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#else
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#define FADDR_BYTEADDR(addr) ((addr) << 0)
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#define FADDR_BITPOS(pos) ((pos) << 10)
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#define FADDR_VAL(addr, pos) (FADDR_BYTEADDR(addr) | FADDR_BITPOS(pos))
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#endif
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#define FDATA_MASK (0xff)
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#define FUSTRAP_O_SECBOOT BIT(23)
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#define FCFG_FDIS BIT(31)
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#define FKEYIND_KVAL BIT(0)
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#define FKEYIND_KSIZE_MASK (0x00000070)
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#define FKEYIND_KSIZE_128 (0x4 << 4)
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#define FKEYIND_KSIZE_192 (0x5 << 4)
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#define FKEYIND_KSIZE_256 (0x6 << 4)
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#define FKEYIND_KIND_MASK (0x000c0000)
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#define FKEYIND_KIND_KEY(indx) ((indx) << 18)
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/* Program cycle initiation values (sequence of two adjacent writes) */
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#define PROGRAM_ARM 0x1
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#define PROGRAM_INIT 0xBF79E5D0
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/* Read cycle initiation value */
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#define READ_INIT 0x02
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/* Value to clean FDATA contents */
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#define FDATA_CLEAN_VALUE 0x01
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#ifdef CONFIG_ARCH_NPCM8XX
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#define NPCM_OTP_ARR_BYTE_SIZE 8192
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#else
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#define NPCM_OTP_ARR_BYTE_SIZE 1024
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#endif
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#define MIN_PROGRAM_PULSES 4
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#define MAX_PROGRAM_PULSES 20
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int fuse_prog_image(u32 bank, uintptr_t address);
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int fuse_program_data(u32 bank, u32 word, u8 *data, u32 size);
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int npcm_otp_select_key(u8 key_index);
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bool npcm_otp_is_fuse_array_disabled(u32 arr);
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void npcm_otp_nibble_parity_ecc_encode(u8 *datain, u8 *dataout, u32 size);
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void npcm_otp_majority_rule_ecc_encode(u8 *datain, u8 *dataout, u32 size);
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#endif
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