u-boot/arch/powerpc
York Sun f5b6fb7c1b powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-05 10:13:50 -06:00
..
cpu powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers 2011-03-05 10:13:50 -06:00
include/asm Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2011-02-09 20:50:26 +01:00
lib Replace "FLASH" strings with "Flash" or "flash" 2011-01-19 00:02:37 +01:00
config.mk Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS 2011-01-25 22:22:30 +01:00