mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
9bf0cbf396
The upstream Linux DSA drivers do not require phy-handle nodes in
the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
the mdio nodes to the u-boot.dtsi file so that future dts file
syncrhonization between Linux and U-Boot don't break networking.
Fixes: 24a7a3c1c0 ("imx8mm: synchronise device tree with linux")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
197 lines
2.7 KiB
Text
197 lines
2.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 Gateworks Corporation
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*/
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#include "imx8mm-venice-u-boot.dtsi"
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&gpio1 {
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uart1_rs422 {
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gpio-hog;
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output-high;
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gpios = <0 GPIO_ACTIVE_HIGH>;
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line-name = "uart1_rs422#";
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};
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uart1rs485 {
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gpio-hog;
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output-high;
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gpios = <3 GPIO_ACTIVE_HIGH>;
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line-name = "uart1_rs485#";
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};
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uart1rs232 {
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gpio-hog;
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output-high;
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gpios = <5 GPIO_ACTIVE_HIGH>;
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line-name = "uart1_rs232#";
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};
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dig1in {
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gpio-hog;
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input;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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line-name = "dig1_in";
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};
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dig1out {
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gpio-hog;
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output-low;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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line-name = "dig1_out";
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};
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};
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&gpio4 {
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uart3_rs232 {
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gpio-hog;
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output-high;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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line-name = "uart3_rs232#";
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};
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uart3_rs422 {
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gpio-hog;
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output-high;
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gpios = <7 GPIO_ACTIVE_HIGH>;
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line-name = "uart3_rs422#";
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};
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uart3_rs485 {
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gpio-hog;
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output-high;
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gpios = <8 GPIO_ACTIVE_HIGH>;
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line-name = "uart3_rs485#";
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};
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uart4_rs485 {
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gpio-hog;
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output-high;
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gpios = <27 GPIO_ACTIVE_HIGH>;
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line-name = "uart4_rs485#";
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};
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sim1det {
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gpio-hog;
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input;
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gpios = <29 GPIO_ACTIVE_HIGH>;
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line-name = "sim1_det";
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};
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sim2det {
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gpio-hog;
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input;
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gpios = <30 GPIO_ACTIVE_HIGH>;
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line-name = "sim2_det";
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};
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};
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&gpio5 {
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dig2out {
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gpio-hog;
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output-low;
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gpios = <3 GPIO_ACTIVE_HIGH>;
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line-name = "dig2_out";
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};
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dig2in {
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gpio-hog;
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input;
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gpios = <4 GPIO_ACTIVE_HIGH>;
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line-name = "dig2_in";
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};
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sim2sel {
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gpio-hog;
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output-low;
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gpios = <5 GPIO_ACTIVE_HIGH>;
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line-name = "sim2_sel";
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};
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uart4_rs232 {
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gpio-hog;
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output-high;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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line-name = "uart4_rs232#";
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};
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uart4_rs422 {
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gpio-hog;
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output-high;
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gpios = <13 GPIO_ACTIVE_HIGH>;
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line-name = "uart4_rs422#";
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};
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};
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&fec1 {
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phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-post-delay = <1>;
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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lan1: port@0 {
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phy-handle = <&sw_phy0>;
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};
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lan2: port@1 {
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phy-handle = <&sw_phy1>;
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};
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lan3: port@2 {
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phy-handle = <&sw_phy2>;
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};
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lan4: port@3 {
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phy-handle = <&sw_phy3>;
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};
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};
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mdios {
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0>;
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compatible = "microchip,ksz-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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sw_phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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sw_phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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sw_phy2: ethernet-phy@2 {
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reg = <0x2>;
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};
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sw_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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};
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};
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};
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&pinctrl_fec1 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
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u-boot,dm-spl;
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};
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&pinctrl_pmic {
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u-boot,dm-spl;
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};
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